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| author | Michael Brown | 2013-04-30 14:36:04 +0200 |
|---|---|---|
| committer | Michael Brown | 2013-04-30 14:42:12 +0200 |
| commit | 592755eccf51c87ca727c2044eee7ffc3266e290 (patch) | |
| tree | e3be3ae927c223dc0d734ee0c4bb7c2217cc9db2 /src/include/ipxe | |
| parent | [pxe] Convert external PXE API errors into iPXE platform-generated errors (diff) | |
| download | ipxe-592755eccf51c87ca727c2044eee7ffc3266e290.tar.gz ipxe-592755eccf51c87ca727c2044eee7ffc3266e290.tar.xz ipxe-592755eccf51c87ca727c2044eee7ffc3266e290.zip | |
[realtek] Allow reaction time between writing RTL_CAPR and reading RTL_CR
Some older RTL8139 chips seem to not immediately update the
RTL_CR.BUFE bit in response to a write to RTL_CAPR. This results in
iPXE seeing a spurious zero-length received packet, and thereafter
being out of sync with the hardware's RX ring offset.
Fix by inserting an extra PCI read cycle after writing to RTL_CAPR, to
give the chip time to react before we next read RTL_CR.
Reported-by: Gelip <mrgelip@gmail.com>
Tested-by: Gelip <mrgelip@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
Diffstat (limited to 'src/include/ipxe')
0 files changed, 0 insertions, 0 deletions