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| author | Michael Brown | 2008-10-29 02:10:33 +0100 |
|---|---|---|
| committer | Michael Brown | 2008-10-29 02:16:52 +0100 |
| commit | 621101c36a61320ba965063658fde0eee94f73e0 (patch) | |
| tree | f129a65d5eac7860a20450d7f671d1a476c924ef /src/include | |
| parent | [phantom] Add CLP settings interface (diff) | |
| download | ipxe-621101c36a61320ba965063658fde0eee94f73e0.tar.gz ipxe-621101c36a61320ba965063658fde0eee94f73e0.tar.xz ipxe-621101c36a61320ba965063658fde0eee94f73e0.zip | |
[romprefix] Further sanity checks for the PCI 3 runtime segment address
This extends the sanity checks on the runtime segment address provided
in %bx, first implemented in commit 5600955.
We now allow the ROM to be placed anywhere above a000:0000 (rather
than c000:0000, as before), since this is the region allowed by the
PCI 3 spec. If the BIOS asks us to place the runtime image such that
it would overlap with the init-time image (which is explicitly
prohibited by the PCI 3 spec), then we assume that the BIOS is faulty
and ignore the provided runtime segment address.
Testing on a SuperMicro BIOS providing overlapping segment addresses
shows that ignoring the provided runtime segment address is safe to do
in these circumstances.
Diffstat (limited to 'src/include')
0 files changed, 0 insertions, 0 deletions