[timer] Rewrite the 8254 Programmable Interval Timer support

The 8254 timer code (used to implement udelay()) has an unknown
provenance.  Rewrite this code to avoid potential licensing
uncertainty.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

6 files changed, 153 insertions, 107 deletions

diff --git a/src/arch/i386/core/rdtsc_timer.c b/src/arch/i386/core/rdtsc_timer.c
index 2f31afc66..f7b4b9af1 100644
--- a/src/arch/i386/core/rdtsc_timer.c
+++ b/src/arch/i386/core/rdtsc_timer.c
@@ -27,7 +27,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
 
 #include <assert.h>
 #include <ipxe/timer.h>
-#include <ipxe/timer2.h>
+#include <ipxe/pit8254.h>
 
 /**
  * Number of TSC ticks per microsecond
@@ -56,10 +56,10 @@ static void rdtsc_udelay ( unsigned long usecs ) {
 			elapsed = ( currticks() - start );
 		} while ( elapsed < ( usecs * rdtsc_ticks_per_usec ) );
 	} else {
-		/* Not yet calibrated; use timer2 and calibrate
+		/* Not yet calibrated; use 8254 PIT and calibrate
 		 * based on result.
 		 */
-		timer2_udelay ( usecs );
+		pit8254_udelay ( usecs );
 		elapsed = ( currticks() - start );
 		rdtsc_ticks_per_usec = ( elapsed / usecs );
 		DBG ( "RDTSC timer calibrated: %ld ticks in %ld usecs "
diff --git a/src/arch/i386/core/timer2.c b/src/arch/i386/core/timer2.c
deleted file mode 100644
index 077866562..000000000
--- a/src/arch/i386/core/timer2.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * arch/i386/core/i386_timer.c
- *
- * Use the "System Timer 2" to implement the udelay callback in
- * the BIOS timer driver. Also used to calibrate the clock rate
- * in the RTDSC timer driver.
- * 
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2, or (at
- * your option) any later version.
- */
-
-FILE_LICENCE ( GPL2_OR_LATER );
-
-#include <stddef.h>
-#include <ipxe/timer2.h>
-#include <ipxe/io.h>
-
-/* Timers tick over at this rate */
-#define TIMER2_TICKS_PER_SEC	1193180U
-
-/* Parallel Peripheral Controller Port B */
-#define	PPC_PORTB	0x61
-
-/* Meaning of the port bits */
-#define	PPCB_T2OUT	0x20	/* Bit 5 */
-#define	PPCB_SPKR	0x02	/* Bit 1 */
-#define	PPCB_T2GATE	0x01	/* Bit 0 */
-
-/* Ports for the 8254 timer chip */
-#define	TIMER2_PORT	0x42
-#define	TIMER_MODE_PORT	0x43
-
-/* Meaning of the mode bits */
-#define	TIMER0_SEL	0x00
-#define	TIMER1_SEL	0x40
-#define	TIMER2_SEL	0x80
-#define	READBACK_SEL	0xC0
-
-#define	LATCH_COUNT	0x00
-#define	LOBYTE_ACCESS	0x10
-#define	HIBYTE_ACCESS	0x20
-#define	WORD_ACCESS	0x30
-
-#define	MODE0		0x00
-#define	MODE1		0x02
-#define	MODE2		0x04
-#define	MODE3		0x06
-#define	MODE4		0x08
-#define	MODE5		0x0A
-
-#define	BINARY_COUNT	0x00
-#define	BCD_COUNT	0x01
-
-static void load_timer2 ( unsigned int ticks ) {
-	/*
-	 * Now let's take care of PPC channel 2
-	 *
-	 * Set the Gate high, program PPC channel 2 for mode 0,
-	 * (interrupt on terminal count mode), binary count,
-	 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
-	 *
-	 * Note some implementations have a bug where the high bits byte
-	 * of channel 2 is ignored.
-	 */
-	/* Set up the timer gate, turn off the speaker */
-	/* Set the Gate high, disable speaker */
-	outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB);
-	/* binary, mode 0, LSB/MSB, Ch 2 */
-	outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT);
-	/* LSB of ticks */
-	outb(ticks & 0xFF, TIMER2_PORT);
-	/* MSB of ticks */
-	outb(ticks >> 8, TIMER2_PORT);
-}
-
-static int timer2_running ( void ) {
-	return ((inb(PPC_PORTB) & PPCB_T2OUT) == 0);
-}
-
-void timer2_udelay ( unsigned long usecs ) {
-	load_timer2 ( ( usecs * TIMER2_TICKS_PER_SEC ) / ( 1000 * 1000 ) );
-	while (timer2_running()) {
-		/* Do nothing */
-	}
-}
diff --git a/src/arch/i386/include/ipxe/bios_timer.h b/src/arch/i386/include/ipxe/bios_timer.h
index f9fc80412..407780a6a 100644
--- a/src/arch/i386/include/ipxe/bios_timer.h
+++ b/src/arch/i386/include/ipxe/bios_timer.h
@@ -15,7 +15,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
 #define TIMER_PREFIX_pcbios __pcbios_
 #endif
 
-#include <ipxe/timer2.h>
+#include <ipxe/pit8254.h>
 
 /**
  * Delay for a fixed number of microseconds
@@ -25,9 +25,9 @@ FILE_LICENCE ( GPL2_OR_LATER );
 static inline __always_inline void
 TIMER_INLINE ( pcbios, udelay ) ( unsigned long usecs ) {
 	/* BIOS timer is not high-resolution enough for udelay(), so
-	 * we use timer2
+	 * we use the 8254 Programmable Interval Timer.
 	 */
-	timer2_udelay ( usecs );
+	pit8254_udelay ( usecs );
 }
 
 /**
diff --git a/src/arch/i386/include/ipxe/timer2.h b/src/arch/i386/include/ipxe/timer2.h
deleted file mode 100644
index 322a3ed59..000000000
--- a/src/arch/i386/include/ipxe/timer2.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _IPXE_TIMER2_H
-#define _IPXE_TIMER2_H
-
-/** @file
- *
- * Timer chip control
- *
- */
-
-FILE_LICENCE ( GPL2_OR_LATER );
-
-extern void timer2_udelay ( unsigned long usecs );
-
-#endif /* _IPXE_TIMER2_H */
diff --git a/src/arch/x86/core/pit8254.c b/src/arch/x86/core/pit8254.c
new file mode 100644
index 000000000..66c71a744
--- /dev/null
+++ b/src/arch/x86/core/pit8254.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2015 Michael Brown <mbrown@fensystems.co.uk>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+#include <assert.h>
+#include <ipxe/io.h>
+#include <ipxe/pit8254.h>
+
+/** @file
+ *
+ * 8254 Programmable Interval Timer
+ *
+ */
+
+/**
+ * Delay for a fixed number of timer ticks using the speaker channel
+ *
+ * @v ticks		Number of timer ticks for which to delay
+ */
+void pit8254_speaker_delay ( unsigned int ticks ) {
+	uint8_t spkr;
+	uint8_t cmd;
+	uint8_t low;
+	uint8_t high;
+
+	/* Sanity check */
+	assert ( ticks <= 0xffff );
+
+	/* Disable speaker, set speaker channel gate input high */
+	spkr = inb ( PIT8254_SPKR );
+	spkr &= ~PIT8254_SPKR_ENABLE;
+	spkr |= PIT8254_SPKR_GATE;
+	outb ( spkr, PIT8254_SPKR );
+
+	/* Program speaker channel to "interrupt" on terminal count */
+	cmd = ( PIT8254_CMD_CHANNEL ( PIT8254_CH_SPKR ) |
+		PIT8254_CMD_ACCESS_LOHI | PIT8254_CMD_OP_TERMINAL |
+		PIT8254_CMD_BINARY );
+	low = ( ( ticks >> 0 ) & 0xff );
+	high = ( ( ticks >> 8 ) & 0xff );
+	outb ( cmd, PIT8254_CMD );
+	outb ( low, PIT8254_DATA ( PIT8254_CH_SPKR ) );
+	outb ( high, PIT8254_DATA ( PIT8254_CH_SPKR ) );
+
+	/* Wait for channel to "interrupt" */
+	do {
+		spkr = inb ( PIT8254_SPKR );
+	} while ( ! ( spkr & PIT8254_SPKR_OUT ) );
+}
diff --git a/src/arch/x86/include/ipxe/pit8254.h b/src/arch/x86/include/ipxe/pit8254.h
new file mode 100644
index 000000000..3af1ae07f
--- /dev/null
+++ b/src/arch/x86/include/ipxe/pit8254.h
@@ -0,0 +1,81 @@
+#ifndef _IPXE_PIT8254_H
+#define _IPXE_PIT8254_H
+
+/** @file
+ *
+ * 8254 Programmable Interval Timer
+ *
+ */
+
+FILE_LICENCE ( GPL2_OR_LATER );
+
+/** IRQ0 channel */
+#define PIT8254_CH_IRQ0 0
+
+/** PC speaker channel */
+#define PIT8254_CH_SPKR 2
+
+/** Timer frequency (1.193182MHz) */
+#define PIT8254_HZ 1193182UL
+
+/** Data port */
+#define PIT8254_DATA(channel) ( 0x40 + (channel) )
+
+/** Mode/command register */
+#define PIT8254_CMD 0x43
+
+/** Select channel */
+#define PIT8254_CMD_CHANNEL(channel) ( (channel) << 6 )
+
+/** Access modes */
+#define PIT8254_CMD_ACCESS_LATCH 0x00	/**< Latch count value command */
+#define PIT8254_CMD_ACCESS_LO	0x10	/**< Low byte only */
+#define PIT8254_CMD_ACCESS_HI	0x20	/**< High byte only */
+#define PIT8254_CMD_ACCESS_LOHI	0x30	/**< Low-byte, high-byte pair */
+
+/* Operating modes */
+#define PIT8254_CMD_OP_TERMINAL	0x00	/**< Interrupt on terminal count */
+#define PIT8254_CMD_OP_ONESHOT	0x02	/**< Hardware re-triggerable one-shot */
+#define PIT8254_CMD_OP_RATE	0x04	/**< Rate generator */
+#define PIT8254_CMD_OP_SQUARE	0x06	/**< Square wave generator */
+#define PIT8254_CMD_OP_SWSTROBE	0x08	/**< Software triggered strobe */
+#define PIT8254_CMD_OP_HWSTROBE	0x0a	/**< Hardware triggered strobe */
+#define PIT8254_CMD_OP_RATE2	0x0c	/**< Rate generator (duplicate) */
+#define PIT8254_CMD_OP_SQUARE2	0x0e	/**< Square wave generator (duplicate)*/
+
+/** Binary mode */
+#define PIT8254_CMD_BINARY 0x00
+
+/** BCD mode */
+#define PIT8254_CMD_BCD 0x01
+
+/** PC speaker control register */
+#define PIT8254_SPKR 0x61
+
+/** PC speaker channel gate */
+#define PIT8254_SPKR_GATE 0x01
+
+/** PC speaker enabled */
+#define PIT8254_SPKR_ENABLE 0x02
+
+/** PC speaker channel output */
+#define PIT8254_SPKR_OUT 0x20
+
+extern void pit8254_speaker_delay ( unsigned int ticks );
+
+/**
+ * Delay for a fixed number of microseconds
+ *
+ * @v usecs		Number of microseconds for which to delay
+ */
+static inline __attribute__ (( always_inline )) void
+pit8254_udelay ( unsigned long usecs ) {
+
+	/* Delays are invariably compile-time constants; force the
+	 * multiplication and division to take place at compilation
+	 * time rather than runtime.
+	 */
+	pit8254_speaker_delay ( ( usecs * PIT8254_HZ ) / 1000000 );
+}
+
+#endif /* _IPXE_PIT8254_H */