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| author | Michael Brown | 2006-05-21 18:02:38 +0200 |
|---|---|---|
| committer | Michael Brown | 2006-05-21 18:02:38 +0200 |
| commit | 9dfb9d84b49106f60f8e5eff2df04c333cc75d97 (patch) | |
| tree | 7d7d54699cae439b603825c8e918343759c8c829 /src | |
| parent | Added (untested) support for ATA devices. This code should be generic (diff) | |
| download | ipxe-9dfb9d84b49106f60f8e5eff2df04c333cc75d97.tar.gz ipxe-9dfb9d84b49106f60f8e5eff2df04c333cc75d97.tar.xz ipxe-9dfb9d84b49106f60f8e5eff2df04c333cc75d97.zip | |
Made the LBA48 example clearer.
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/gpxe/ata.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/include/gpxe/ata.h b/src/include/gpxe/ata.h index 3cc01cf8c..5aeb82e6c 100644 --- a/src/include/gpxe/ata.h +++ b/src/include/gpxe/ata.h @@ -20,14 +20,14 @@ * set" (LBA48), in which case each of these byte-wide registers is * actually a two-entry FIFO, and the "previous" byte pushed into the * FIFO is used as the corresponding high-order byte. So, to set up - * the 48-bit address 0x12345678abcd, you would issue + * the 48-bit address 0x123456abcdef, you would issue * * 0x56 -> LBA Low register - * 0xcd -> LBA Low register + * 0xef -> LBA Low register * 0x34 -> LBA Mid register - * 0xab -> LBA Mid register + * 0xcd -> LBA Mid register * 0x12 -> LBA High register - * 0x78 -> LBA High register + * 0xab -> LBA High register * * This structure encapsulates this information by providing a single * 64-bit integer in native byte order, unioned with bytes named so |