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* [init] Show startup and shutdown function names in debug messagesMichael Brown2019-01-251-0/+1
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [build] Avoid implicit-fallthrough warnings on GCC 7Michael Brown2017-03-291-0/+2
| | | | | | Reported-by: Vinson Lee <vlee@freedesktop.org> Reported-by: Liang Yan <lyan@suse.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bzimage] Fix page alignment of initrd imagesMichael Brown2016-10-291-3/+5
| | | | | | | | | | | | The initrd_addr_max field represents the highest byte address that may be used to hold initrd images, and is therefore almost certainly not aligned to a page boundary: a typical value might be 0x7fffffff. Fix the address calculations to ensure that the initrd images are always aligned to a page boundary. Reported-by: Sitsofe Wheeler <sitsofe@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [pxe] Disable interrupts on the PIC before starting NBPMichael Brown2016-07-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | Some BIOSes (observed with an HP Gen9) seem to spuriously enable interrupts at the PIC. This causes problems with NBPs such as GRUB which use the UNDI API (thereby enabling interrupts on the NIC) without first hooking an interrupt service routine. In this situation, the interrupt will end up being handled by the default BIOS ISR, which will typically just send an EOI and return. Since nothing in this handler causes the NIC to deassert the interrupt, this will result in an interrupt storm. Entertainingly, some BIOSes are immune to this problem because the default ISR sends the EOI only to the slave PIC; this effectively disables the interrupt. Work around this problem by disabling the interrupt on the PIC before invoking the PXE NBP. An NBP that expects to make use of interrupts will need to be configuring the PIC anyway, so it is probably safe to assume that it will explicitly reenable the interrupt. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [comboot] Support COMBOOT in 64-bit buildsMichael Brown2016-04-152-0/+635
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Make uses of REAL_CODE() and PHYS_CODE() 64-bit cleanMichael Brown2016-02-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | On a 64-bit CPU, any modification of a register by 32-bit or 16-bit code will destroy the invisible upper 32 bits of the corresponding 64-bit register. For example: a 32-bit "pushl %eax" followed by a "popl %eax" will zero the upper half of %rax. This differs from the treatment of upper halves of 32-bit registers by 16-bit code: a "pushw %ax" followed by a "popw %ax" will leave the upper 16 bits of %eax unmodified. Inline assembly generated using REAL_CODE() or PHYS_CODE() will therefore have to preserve the upper halves of all registers, to avoid clobbering registers that gcc expects to be preserved. Output operands from REAL_CODE() and PHYS_CODE() assembly may therefore contain undefined values in the upper 32 bits. Fix by using explicit variable widths (e.g. uint32_t) for non-discarded output operands, to ensure that undefined values in the upper 32 bits of 64-bit registers are ignored. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [bios] Add bin-x86_64-pcbios build platformMichael Brown2016-02-168-0/+2492
Move most arch/i386 files to arch/x86, and adjust the contents of the Makefiles and the include/bits/*.h headers to reflect the new locations. This patch makes no substantive code changes, as can be seen using a rename-aware diff (e.g. "git show -M5"). This patch does not make the pcbios platform functional for x86_64; it merely allows it to compile without errors. Signed-off-by: Michael Brown <mcb30@ipxe.org>