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* Merge branch 'master' into openslxopenslxSimon Rettberg2026-01-28251-3673/+8158
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| * [prefix] Make unlzma.S compatible with 386 class CPUsJaromir Capik2026-01-251-2/+4
| * [build] Mark known reviewed files as permitted for UEFI Secure BootMichael Brown2026-01-145-0/+5
| * [build] Mark core files as permitted for UEFI Secure BootMichael Brown2026-01-1437-0/+37
| * [crypto] Allow for zero-length big integer literalsMichael Brown2025-12-291-2/+6
| * [pci] Allow probing permission to vary by rangeMichael Brown2025-11-252-2/+4
| * [pci] Use linker tables for runtime selectable PCI APIsMichael Brown2025-11-247-306/+2Star
| * [pci] Allow PCI configuration space access mechanism to vary by rangeMichael Brown2025-11-241-48/+121
| * [arm] Avoid unaligned accesses for memcpy() and memset()Michael Brown2025-11-191-74/+100
| * [ioapi] Allow iounmap() to be called for port I/O addressesMichael Brown2025-11-053-10/+20
| * [uart] Support 16550 UARTs accessed via either MMIO or port I/OMichael Brown2025-11-041-2/+2
| * [ioapi] Provide combined MMIO and port I/O accessorsMichael Brown2025-11-041-0/+69
| * [riscv] Correct page table stride calculationMichael Brown2025-10-271-1/+1
| * [librm] Correct page table stride calculationMichael Brown2025-10-271-1/+1
| * [cmdline] Show commands in alphabetical orderMichael Brown2025-08-062-14/+3Star
| * [riscv] Place explicitly zero-initialised variables in the .data sectionMichael Brown2025-07-301-0/+7
| * [riscv] Allow for poisoning .bss section before early initialisationMichael Brown2025-07-301-0/+51
| * [undi] Assume that legacy interrupts are broken for any PCIe deviceMichael Brown2025-07-241-3/+21
| * [pxeprefix] Display PCI vendor and device ID in PXE startup bannerMichael Brown2025-07-231-0/+8
| * [init] Show initialisation function names in debug messagesMichael Brown2025-07-1510-0/+10
| * [riscv] Ensure coherent DMA allocations do not cross cacheline boundariesMichael Brown2025-07-111-0/+15
| * [riscv] Support the standard Svpbmt extension for page-based memory typesMichael Brown2025-07-111-0/+20
| * [riscv] Create coherent DMA mapping of 32-bit address space on demandMichael Brown2025-07-114-70/+77
| * [riscv] Use 1GB pages for I/O device mappingsMichael Brown2025-07-111-9/+9
| * [riscv] Invalidate data cache on completed RX DMA buffersMichael Brown2025-07-102-16/+47
| * [riscv] Add optimised TCP/IP checksummingMichael Brown2025-07-102-0/+153
| * [riscv] Provide a DMA API implementation for RISC-V bare-metal systemsMichael Brown2025-07-096-12/+221
| * [riscv] Support explicit cache management operations on I/O buffersMichael Brown2025-07-072-0/+273
| * [riscv] Add support for detecting T-Head vendor extensionsMichael Brown2025-07-073-0/+90
| * [riscv] Create coherent DMA mapping for low 4GB of address spaceMichael Brown2025-07-041-2/+30
| * [riscv] Construct invariant portions of page table outside the loopMichael Brown2025-07-041-48/+49
| * [build] Allow for the existence of small-data sectionsMichael Brown2025-06-243-0/+18
| * [pxe] Use a weak symbol for isapnp_read_portMichael Brown2025-06-241-1/+1
| * [dwuart] Read input clock frequency from the device treeMichael Brown2025-06-231-0/+1
| * [riscv] Inhibit SBI console when a serial console is activeMichael Brown2025-06-231-0/+12
| * [riscv] Serialise MMIO accesses with respect to each otherMichael Brown2025-06-221-4/+8
| * [uart] Allow for dynamically registered 16550 UARTsMichael Brown2025-06-223-17/+16Star
| * [uart] Allow for the existence of non-16550 UARTsMichael Brown2025-06-204-74/+102
| * [riscv] Write SBI console output to early UART, if enabledMichael Brown2025-06-122-0/+31
| * [riscv] Maximise barrier effects of memory fencesMichael Brown2025-06-121-1/+1
| * [riscv] Support T-Head CPUs using non-standard Memory Attribute ExtensionMichael Brown2025-06-021-7/+59
| * [riscv] Do not set executable bit in early UART page mappingMichael Brown2025-06-021-1/+1
| * [riscv] Add fences around early UART writesMichael Brown2025-06-021-0/+2
| * [riscv] Zero SATP after any failed attempt to enable pagingMichael Brown2025-06-021-5/+7
| * [riscv] Add support for a SiFive-compatible early UARTMichael Brown2025-05-271-2/+33
| * [riscv] Support mapping early UARTs outside of the identity mapMichael Brown2025-05-271-4/+48
| * [riscv] Add support for writing prefix debug messages direct to a UARTMichael Brown2025-05-271-0/+79
| * [riscv] Create macros for writing characters to the debug consoleMichael Brown2025-05-271-17/+62
| * [riscv] Ignore riscv,isa property in favour of direct CSR testingMichael Brown2025-05-262-13/+5Star
| * [image] Use image name rather than pointer value in all debug messagesMichael Brown2025-05-264-66/+65Star
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