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* [mii] Separate concepts of MII interface and MII deviceMichael Brown2018-04-191-1/+3
| | | | | | | | | | | | | We currently have no generic concept of a PHY address, since all existing implementations simply hardcode the PHY address within the MII access methods. A bit-bashing MII interface will need to be provided with an explicit PHY address in order to generate the correct waveform. Allow for this by separating out the concept of a MII device (i.e. a specific PHY address attached to a particular MII interface). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [legal] Relicense files under GPL2_OR_LATER_OR_UBDLMichael Brown2015-03-021-1/+1
| | | | | | | Relicense files for which I am the sole author (as identified by util/relicense.pl). Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Clear bit 24 of RCRMichael Brown2014-03-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | On an Asus Z87-K motherboard with an onboard 8168 NIC, booting into Windows 7 and then warm rebooting into iPXE results in a broken RX datapath: packets can be transmitted successfully but garbage is received. A cold reboot clears the problem. A dump of the PHY registers reveals only one difference: in the failure case the bits ADVERTISE_PAUSE_CAP and ADVERTISE_PAUSE_ASYM are cleared. Explicitly setting these bits does not fix the problem. A dump of the MAC registers reveals a few differences, of which the most obvious culprit is the undocumented bit 24 of the Receive Configuration Register (RCR), which is set in the failure case. Explicitly clearing this bit does fix the problem. Reported-by: Sebastian Nielsen <ipxe@sebbe.eu> Reported-by: Oliver Rath <rath@mglug.de> Debugged-by: Sebastian Nielsen <ipxe@sebbe.eu> Tested-by: Sebastian Nielsen <ipxe@sebbe.eu> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Include link status register details in debug messagesMichael Brown2014-03-041-0/+13
| | | | Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Allow extra space in RX buffersMichael Brown2013-07-151-1/+2
| | | | | | | | | | | Some hardware (observed with an onboard RTL8168) will erroneously report a buffer overflow error if the received packet exactly fills the receive buffer. Fix by adding an extra four bytes of padding to each receive buffer. Debugged-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Use ID word to detect EEPROM presenceMichael Brown2013-04-281-0/+6
| | | | | | | | | | | | | | | | | Some onboard RTL8169 NICs seem to leave the EEPROM pins disconnected. The existing is_valid_ether_addr() test will not necessarily catch this, since it expects a missing EEPROM to show up as a MAC address of 00:00:00:00:00:00 or ff:ff:ff:ff:ff:ff. When the EEPROM pins are floating the MAC address may read as e.g. 00:00:00:00:0f:00, which will not be detected as invalid. Check the ID word in the first two bytes of the EEPROM (which should have the value 0x8129 for all RTL8139 and RTL8169 chips), and use this to determine whether or not an EEPROM is present. Reported-by: Carl Karsten <carl@nextdayvideo.com> Tested-by: Carl Karsten <carl@nextdayvideo.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Force EEPROM CS low before disabling EEPROM access modeMichael Brown2012-08-241-2/+3
| | | | | | | | | | | | | Some RTL8169 cards seem to drive the EEPROM CS line high (i.e. active) when 9346CR.EEM is set to "normal operating mode", with the result that the CS line is never deasserted. The symptom of this is that the first read from the EEPROM will work, while all subsequent reads will return garbage data. Reported-by: Thomas Miletich <thomas.miletich@gmail.com> Debugged-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Use explicit value for TCR.MXDMAMichael Brown2012-08-231-0/+6
| | | | | | | | | | Some RTL8169 cards (observed with an RTL8169SC) power up with TCR.MXDMA set to 16 bytes. While this does not prevent proper operation, it almost certainly degrades performance. Fix by explicitly setting TCR.MXDMA to "unlimited". Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Use explicit values for RCR.RXFTH and RCR.MXDMAMichael Brown2012-08-231-0/+6
| | | | | | | | Some RTL8169 cards (observed with an RTL8169SC) power up with invalid values in RCR.RXFTH and RCR.MXDMA, causing receive DMA to fail. Fix by setting explicit values for both fields. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Support RTL8139 cards within generic Realtek driverMichael Brown2012-04-281-17/+85
| | | | | | | | | | | | | | | | RTL8139C+ cards use essentially the same datapath as RTL8169, which is zerocopy and 64-bit capable. Older RTL8139 cards use a single receive ring buffer rather than a descriptor ring, but still share substantial amounts of functionality with RTL8169. Include support for RTL8139 cards within the generic Realtek driver, since there is no way to differentiate between RTL8139 and RTL8139C+ cards based on the PCI IDs alone. Many thanks to all the people who worked on the rtl8139 driver over the years. Signed-off-by: Michael Brown <mcb30@ipxe.org>
* [realtek] Replace driver for Realtek Gigabit NICsMichael Brown2012-04-181-0/+205
Tested-by: Thomas Miletich <thomas.miletich@gmail.com> Debugged-by: Thomas Miletich <thomas.miletich@gmail.com> Tested-by: Robin Smidsrød <robin@smidsrod.no> Signed-off-by: Michael Brown <mcb30@ipxe.org>