first attempt to write to a file was sucessful, but not the optimal solution

4 files changed, 99 insertions, 126 deletions

diff --git a/efi_memtest/memtest86+/bios/init.c b/efi_memtest/memtest86+/bios/init.c
index 32bff7f..1cb3b97 100644
--- a/efi_memtest/memtest86+/bios/init.c
+++ b/efi_memtest/memtest86+/bios/init.c
@@ -627,16 +627,16 @@ void smp_default_mode(void)
 {
 	int i, result;
 	char *cpupsn = cpu_id.brand_id.char_array;
-  char *disabledcpu[] = { "Opteron", "Xeon", "EPYC", "Genuine Intel" };
+  	char *disabledcpu[] = { "Opteron", "Xeon", "EPYC", "Genuine Intel" };
   
-  for(i = 0; i < 3; i++) 
-  {
-      result = mt86_strstr(cpupsn , disabledcpu[i]);
-      if(result != -1) { vv->fail_safe |= 0b10; }
-  }
+  	for(i = 0; i < 3; i++) 
+  	{
+      	result = mt86_strstr(cpupsn , disabledcpu[i]);
+      	if(result != -1) { vv->fail_safe |= 0b10; }
+  	}
   
-  // For 5.01 release, SMP disabled by defualt by config.h toggle
-  if(CONSERVATIVE_SMP) { vv->fail_safe |= 0b10; }
+  	// For 5.01 release, SMP disabled by defualt by config.h toggle
+  	if(CONSERVATIVE_SMP) { vv->fail_safe |= 0b10; }
   	
 }
 
diff --git a/efi_memtest/memtest86+/efi/init.c b/efi_memtest/memtest86+/efi/init.c
index 2e17f66..1eb8ebc 100644
--- a/efi_memtest/memtest86+/efi/init.c
+++ b/efi_memtest/memtest86+/efi/init.c
@@ -41,9 +41,9 @@ ulong extclock;
 
 ulong memspeed(ulong src, ulong len, int iter);
 static void cpu_type(void);
-//static int cpuspeed(void);
+static int cpuspeed(void);
 static void get_cache_size();
-//static void cpu_cache_speed();
+static void cpu_cache_speed();
 void get_cpuid();
 int beepmode;
 extern short dmi_initialized;
@@ -275,7 +275,7 @@ void init(void)
 
     cpu_type();
 
-    //cpu_cache_speed();
+    cpu_cache_speed();
 
     /* Check fail safe */	
 /*    failsafe(5000, 0x3B);
@@ -311,7 +311,7 @@ void init(void)
     if(vv->check_temp > 0 && !(vv->fail_safe & 4))
     {
         cprint(LINE_CPU, 26, "|  CPU Temp");
-        cprint(LINE_CPU+1, 26, "|      øC");
+        cprint(LINE_CPU+1, 26, "|      øC");
     }
 	
     beep(600);
@@ -629,16 +629,16 @@ void smp_default_mode(void)
 {
 	int i, result;
 	char *cpupsn = cpu_id.brand_id.char_array;
-  char *disabledcpu[] = { "Opteron", "Xeon", "EPYC", "Genuine Intel" };
+  	char *disabledcpu[] = { "Opteron", "Xeon", "EPYC", "Genuine Intel" };
   
-  for(i = 0; i < 3; i++) 
-  {
-      result = mt86_strstr(cpupsn , disabledcpu[i]);
-      if(result != -1) { vv->fail_safe |= 0b10; }
-  }
+  	for(i = 0; i < 3; i++) 
+  	{
+      	result = mt86_strstr(cpupsn , disabledcpu[i]);
+      	if(result != -1) { vv->fail_safe |= 0b10; }
+  	}
   
-  // For 5.01 release, SMP disabled by defualt by config.h toggle
-  if(CONSERVATIVE_SMP) { vv->fail_safe |= 0b10; }
+  	// For 5.01 release, SMP disabled by defualt by config.h toggle
+  	if(CONSERVATIVE_SMP) { vv->fail_safe |= 0b10; }
   	
 }
 
@@ -647,21 +647,20 @@ void smp_default_mode(void)
  */
 void cpu_type(void)
 {
-	dssfgdg
 	/* If we can get a brand string use it, and we are done */
-/*	if (cpu_id.max_xcpuid >= 0x80000004) {
-		cprint(0, COL_MID, cpu_id.brand_id.char_array);
+	if (cpu_id.max_xcpuid >= 0x80000004) {
+		cprint(0, COL_MID, cpu_id.brand_id.char_array); // TODO this hides an other cprint output
 		//If we have a brand string, maybe we have an IMC. Check that.
 		detect_imc();
-		smp_default_mode();	
+		smp_default_mode();
 		return;
-	}*/
+	}
 
 	/* The brand string is not available so we need to figure out 
 	 * CPU what we have */
-/*	switch(cpu_id.vend_id.char_array[0]) {
-*/	/* AMD Processors */
-	/*case 'A':
+	switch(cpu_id.vend_id.char_array[0]) {
+	/* AMD Processors */
+	case 'A':
 		switch(cpu_id.vers.bits.family) {
 		case 4:
 			switch(cpu_id.vers.bits.model) {
@@ -683,9 +682,9 @@ void cpu_type(void)
 			case 15:
 				cprint(0, COL_MID, "AMD 5x86-WB");
 				break;
-			}*/
+			}
 			/* Since we can't get CPU speed or cache info return */
-			/*return;
+			return;
 		case 5:
 			switch(cpu_id.vers.bits.model) {
 			case 0:
@@ -737,35 +736,35 @@ void cpu_type(void)
 				break;
 			case 3:
 			case 7:
-				cprint(0, COL_MID, "AMD Duron");*/
+				cprint(0, COL_MID, "AMD Duron");
 				/* Duron stepping 0 CPUID for L2 is broken */
 				/* (AMD errata T13)*/
-			/*	if (cpu_id.vers.bits.stepping == 0) { *//* stepping 0 */
+				if (cpu_id.vers.bits.stepping == 0) { /* stepping 0 */
 					/* Hard code the right L2 size */
-					/*l2_cache = 64;
+					l2_cache = 64;
 				} else {
 				}
 				break;
 			}
-			break;*/
+			break;
 
 			/* All AMD family values >= 10 have the Brand ID
 			 * feature so we don't need to find the CPU type */
-	/*	}
-		break;*/
+		}
+		break;
 
 	/* Intel or Transmeta Processors */
-	/*case 'G':
-		if ( cpu_id.vend_id.char_array[7] == 'T' ) {*/ /* GenuineTMx86 */
-			/*if (cpu_id.vers.bits.family == 5) {
+	case 'G':
+		if ( cpu_id.vend_id.char_array[7] == 'T' ) { /* GenuineTMx86 */
+			if (cpu_id.vers.bits.family == 5) {
 				cprint(0, COL_MID, "TM 5x00");
 			} else if (cpu_id.vers.bits.family == 15) {
 				cprint(0, COL_MID, "TM 8x00");
 			}
 			l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
 			l2_cache = (cpu_id.cache_info.ch[11]*256) + cpu_id.cache_info.ch[10];
-		} else {	*/			/* GenuineIntel */
-			/*if (cpu_id.vers.bits.family == 4) {
+		} else {			/* GenuineIntel */
+			if (cpu_id.vers.bits.family == 4) {
 			switch(cpu_id.vers.bits.model) {
 			case 0:
 			case 1:
@@ -792,9 +791,9 @@ void cpu_type(void)
 			case 9:
 				cprint(0, COL_MID, "Intel 486DX4-WB");
 				break;
-			}*/
+			}
 			/* Since we can't get CPU speed or cache info return */
-			/*return;
+			return;
 		}
 
 
@@ -916,19 +915,19 @@ void cpu_type(void)
 		    }
 
 		}
-		break;*/
+		break;
 
 	/* VIA/Cyrix/Centaur Processors with CPUID */
-/*	case 'C':
-		if ( cpu_id.vend_id.char_array[1] == 'e' ) {*/ /* CentaurHauls */
-			/*l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
+	case 'C':
+		if ( cpu_id.vend_id.char_array[1] == 'e' ) { /* CentaurHauls */
+			l1_cache = cpu_id.cache_info.ch[3] + cpu_id.cache_info.ch[7];
 			l2_cache = cpu_id.cache_info.ch[11];
 			switch(cpu_id.vers.bits.family){
 			case 5:
 				cprint(0, COL_MID, "Centaur 5x86");
 				break;
-			case 6:*/ // VIA C3
-				/*switch(cpu_id.vers.bits.model){
+			case 6: // VIA C3
+				switch(cpu_id.vers.bits.model){
 				default:
 				    if (cpu_id.vers.bits.stepping < 8) {
 					cprint(0, COL_MID, "VIA C3 Samuel2");
@@ -953,8 +952,8 @@ void cpu_type(void)
 					break;
 				}
 			}
-		} else {	*/			/* CyrixInstead */
-			/*switch(cpu_id.vers.bits.family) {
+		} else {				/* CyrixInstead */
+			switch(cpu_id.vers.bits.family) {
 			case 5:
 				switch(cpu_id.vers.bits.model) {
 				case 0:
@@ -966,8 +965,8 @@ void cpu_type(void)
 				}
 				return;
 
-			case 6: */// VIA C3
-				/*switch(cpu_id.vers.bits.model) {
+			case 6: // VIA C3
+				switch(cpu_id.vers.bits.model) {
 				case 6:
 					cprint(0, COL_MID, "Cyrix III");
 					break;
@@ -984,18 +983,18 @@ void cpu_type(void)
 				case 9:
 					cprint(0, COL_MID, "VIA C3 Nehemiah");
 					break;
-				}*/
+				}
 				// L1 = L2 = 64 KB from Cyrix III to Nehemiah
-				/*l1_cache = 64;
+				l1_cache = 64;
 				l2_cache = 64;
 				break;
 			}
 		}
-		break;*/
+		break;
 	/* Unknown processor */
-	/*default:*/
+	default:
 		/* Make a guess at the family */
-		/*switch(cpu_id.vers.bits.family) {
+		switch(cpu_id.vers.bits.family) {
 		case 5:
 			cprint(0, COL_MID, "586");
 		case 6:
@@ -1003,50 +1002,50 @@ void cpu_type(void)
 		default:
 			cprint(0, COL_MID, "Unidentified Processor");
 		}
-	}*/
+	}
 }
 
 #define STEST_ADDR 0x100000	/* Measure memory speed starting at 1MB */
 
 /* Measure and display CPU and cache sizes and speeds */
-/*void cpu_cache_speed()
+void cpu_cache_speed()
 {
 	int i, off = 4;
 	ulong speed;
-*/
+
 
 	/* Print CPU speed */
-	/*if ((speed = cpuspeed()) > 0) {
+	if ((speed = cpuspeed()) > 0) {
 		if (speed < 999499) {
-			speed += 50;*/ /* for rounding *//*
+			speed += 50; /* for rounding */
 			cprint(1, off, "    . MHz");
 			dprint(1, off+1, speed/1000, 3, 1);
-			dprint(1, off+5, (speed/100)%10, 1, 0);*/
-	/*	} else {
-			speed += 500;*/ /* for rounding */
-		/*	cprint(1, off, "      MHz");
+			dprint(1, off+5, (speed/100)%10, 1, 0);
+		} else {
+			speed += 500; /* for rounding */
+			cprint(1, off, "      MHz");
 			dprint(1, off, speed/1000, 5, 0);
 		}
 		extclock = speed;
-	}*/
+	}
 
 	/* Print out L1 cache info */
 	/* To measure L1 cache speed we use a block size that is 1/4th */
 	/* of the total L1 cache size since half of it is for instructions */
-/*	if (l1_cache) {
+	if (l1_cache) {
 		cprint(2, 0, "L1 Cache:     K  ");
 		dprint(2, 11, l1_cache, 3, 0);
 		if ((speed=memspeed(STEST_ADDR, (l1_cache/2)*1024, 200))) {
 			cprint(2, 16, "       MB/s");
 			dprint(2, 16, speed, 6, 0);
 		}
-	}*/
+	}
 
 	/* Print out L2 cache info */
 	/* We measure the L2 cache speed by using a block size that is */
 	/* the size of the L1 cache.  We have to fudge if the L1 */
 	/* cache is bigger than the L2 */
-/*	if (l2_cache) {
+	if (l2_cache) {
 		cprint(3, 0, "L2 Cache:     K  ");
 		dprint(3, 10, l2_cache, 4, 0);
 
@@ -1059,17 +1058,17 @@ void cpu_type(void)
 			cprint(3, 16, "       MB/s");
 			dprint(3, 16, speed, 6, 0);
 		}
-	}*/
+	}
 	/* Print out L3 cache info */
 	/* We measure the L3 cache speed by using a block size that is */
 	/* 2X the size of the L2 cache. */
-/*
+
 	if (l3_cache) 
 	{
 		cprint(4, 0, "L3 Cache:     K  ");
-   	aprint(4, 10, l3_cache/4);*/
+   	aprint(4, 10, l3_cache/4);
     //dprint(4, 10, l3_cache, 4, 0);
-    /*
+    
     		i = l2_cache*2;
     
     		if ((speed=memspeed(STEST_ADDR, i*1024, 150))) {
@@ -1077,7 +1076,7 @@ void cpu_type(void)
     			dprint(4, 16, speed, 6, 0);
     		}
    }
-}*/
+}
 
 /* Measure and display memory speed, multitasked using all CPUs */
 ulong spd[MAX_CPUS];
@@ -1108,7 +1107,7 @@ void get_mem_speed(int me, int ncpus)
 #define TICKS 59659	/* 50 ms */
 
 /* Returns CPU clock in khz */
-/*ulong stlow, sthigh;
+ulong stlow, sthigh;
 static int cpuspeed(void)
 {
 	int loops;
@@ -1117,14 +1116,14 @@ static int cpuspeed(void)
 	if (cpu_id.fid.bits.rdtsc == 0 ) {
 		return(-1);
 	}
-*/
+
 	/* Setup timer */
-	/*outb((inb(0x61) & ~0x02) | 0x01, 0x61);
+	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
 	outb(0xb0, 0x43); 
 	outb(TICKS & 0xff, 0x42);
 	outb(TICKS >> 8, 0x42);
 
-	asm __volatile__ ("rdtsc":"=a" (stlow),"=d" (sthigh));
+ 	asm __volatile__ ("rdtsc":"=a" (stlow),"=d" (sthigh));
 
 	loops = 0;
 	do {
@@ -1137,9 +1136,9 @@ static int cpuspeed(void)
 		"sbbl sthigh,%%edx\n\t" \
 		:"=a" (end_low), "=d" (end_high)
 	);
-*/
+
 	/* Make sure we have a credible result */
-	/*if (loops < 4 || end_low < 50000) {
+	if (loops < 4 || end_low < 50000) {
 		return(-1);
 	}
 	vv->clks_msec = end_low/50;
@@ -1147,7 +1146,7 @@ static int cpuspeed(void)
 	if (tsc_invariable) end_low = correct_tsc(end_low);
 
 	return(vv->clks_msec);
-}*/
+}
 
 /* Measure cache speed by copying a block of memory. */
 /* Returned value is kbytes/second */
diff --git a/efi_memtest/memtest86+/efi/logger.c b/efi_memtest/memtest86+/efi/logger.c
index dfc537b..433b19e 100644
--- a/efi_memtest/memtest86+/efi/logger.c
+++ b/efi_memtest/memtest86+/efi/logger.c
@@ -2,47 +2,8 @@
 #include "Library/UefiLib.h"
 #include "logger.h"
 
-
 volatile short logflag = 0;
 
-/*UINTN
-InternalPrint (
-  IN  CONST CHAR16                     *Format,
-  IN  EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL  *Console,
-  IN  VA_LIST                          Marker
-  )
-{
-  EFI_STATUS  Status;
-  UINTN       Return;
-  CHAR16      *Buffer;
-  UINTN       BufferSize;
-
-  ASSERT (Format != NULL);
-  ASSERT (((UINTN) Format & BIT0) == 0);
-  ASSERT (Console != NULL);
-
-  BufferSize = (PcdGet32 (PcdUefiLibMaxPrintBufferSize) + 1) * sizeof (CHAR16);
-
-  Buffer = (CHAR16 *) AllocatePool(BufferSize);
-  ASSERT (Buffer != NULL);
-
-  Return = UnicodeVSPrint (Buffer, BufferSize, Format, Marker);
-
-  if (Console != NULL && Return > 0) {
-    //
-    // To be extra safe make sure Console has been initialized
-    //
-    Status = Console->OutputString (Console, Buffer);
-    if (EFI_ERROR (Status)) {
-      Return = 0;
-    }
-  }
-
-  FreePool (Buffer);
-
-  return Return;
-}*/
-
 void int_to_charr(uint32_t num, char* arr) { // TODO test corner cases
   uint32_t n = num;
   char buffer[10];
diff --git a/memtestEDK/Memtest/ProtocolInformation/ProtocolInformation.c b/memtestEDK/Memtest/ProtocolInformation/ProtocolInformation.c
index 59e424f..547c91e 100644
--- a/memtestEDK/Memtest/ProtocolInformation/ProtocolInformation.c
+++ b/memtestEDK/Memtest/ProtocolInformation/ProtocolInformation.c
@@ -166,10 +166,10 @@ UefiMain (
               root, 
               &token,
               L"log",
-              EFI_FILE_MODE_READ,
-              EFI_FILE_READ_ONLY | EFI_FILE_HIDDEN | EFI_FILE_SYSTEM);
+              EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE,
+              0);
 
-            UINTN fileSize = 50;
+            UINTN fileSize = 50; // TODO get the actual size
             CHAR16* fileBuffer = NULL;
             efiStatus = bs->AllocatePool(EfiLoaderData, (UINTN) (fileSize) , (void **)&fileBuffer);
 
@@ -177,9 +177,22 @@ UefiMain (
             Print(L"Status after file read: %r\n", efiStatus);
             Print(L"File Size: %d\n", fileSize);
             Print(L"File Buffer Pointer: %p\n", fileBuffer);
-
             Print(L"File Content: %a\n", fileBuffer);
 
+            UINT64 currPos;
+
+            token->GetPosition(token, &currPos);
+            Print(L"Current File Position: %d\n", currPos);
+
+            fileBuffer[0] = (CHAR16) 'X';
+            Print(L"New file Buffer: %a\n", fileBuffer);
+
+            token->SetPosition(token, 0);
+
+            efiStatus = token->Write(token, &fileSize, fileBuffer);
+
+            Print(L"Status after file write: %r\n", efiStatus);
+
 
 /*
           EFI_FILE_OPEN         Open;