created new directory for general information

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diff --git a/documentation/general/APIC b/documentation/general/APIC
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+APIC - Advanced Programmable Interrupt Controller (Wikipedia)
+
+Particularly enabling the construction of multiprocessor systems.
+One of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.
+
+Split architecture design: local component (LAPIC) and optional I/O APIC on a system bus.
+
+Intel: One LAPIC in each CPU and typically one I/O APIC for each peripheral bus in the system.
+
+INTEGRATED LOCAL APICS
+-----------------------
+Manage all external interrupts for some specific processor in an SMP system.
+In addition, able to accept and generate inter-processur interrupts (IPIs) between LAPICS.
+
diff --git a/documentation/general/ATA_ATAPI b/documentation/general/ATA_ATAPI
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+ATA - AT Attachment
+--------------------
+
+standard for parallel data transfer between hard disc storages and the corresponding interface of a computer.
+
+
+ATAPI - AT Attachment Packet Interface
+---------------------------------------
+uses this interface and expands the protocol st it can transport SCSI-pakets. Additionally supports
diff --git a/documentation/general/MMX b/documentation/general/MMX
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+MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel.  (Wikipedia)
+
+Defines eight registers, MM0 to MM7 and operations that operate on them. Each register: 64 bits wide and can hold either 64-bit integers
+or multiple smaller integers in a packed format.
+
+MMX provides only integer operations.
+To avoid compatibility problems with the context switch mechanisms in existing operating systems, the MMX registers are aliases for the existing x87 FPU registers, which context switches would already save and restore. Unlike the x87 registers, which behave like a stack, the MMX registers are each directly addressable (random access). 
+
+Any operation involving the floating point stack might also affect the MMX registers and vice versa, so this aliasing makes it difficult to work with floating point and SIMD operations in the same application.[10] To maximize performance, programmers often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible. 
diff --git a/documentation/general/PAE b/documentation/general/PAE
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+PAE - Physical Address Extension (Wikipedia)
+---------------------------------------------
+Memory management feature for the x86 architecture, 
+
+Page-table hierarchy of three levels (instead of two), with table entries of 64 bits instead of 32,
+allowing CPUs to directly access a physical address space larger than 4 gigabytes.
+
+Page-table structure used by x86-64 CPUs when operating in long mode firther extends page table hierarchy to
+four levels, extending the virtual address space and uses additional physical address bits at all levels of the page table, extending the physical address space. Also uses the topmost bit of 64bit page table entry as a no-executive or "NX" bit, indicating that code cannot be executed from the associated page.
+
+With PAE, the page table entry of the x86 architecture is enlarged from 32 to 64 bits. This allows more room for the physical page address, or "page frame number" field, in the page table entry. In the initial implementations of PAE the page frame number field was expanded from 20 to 24 bits. The size of the "byte offset" from the address being translated is still 12 bits, so total physical address size increases from 32 bits to 36 bits (i.e. from 20+12 to 24+12). This increased the physical memory that is theoretically addressable by the CPU from 4 GB to 64 GB. 
diff --git a/documentation/general/SSE b/documentation/general/SSE
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