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| author | Regina König | 2020-07-24 01:27:01 +0200 |
|---|---|---|
| committer | Regina König | 2020-07-24 01:27:01 +0200 |
| commit | 553422898c9b07bf068dfbb650ce2b30b84b8e8e (patch) | |
| tree | 1d4e79a2b730642f4cb86afe2a7be96cb5160ca0 /documentation | |
| parent | Added other memtest86+ files to SingleComponents (diff) | |
| download | memtest86-553422898c9b07bf068dfbb650ce2b30b84b8e8e.tar.gz memtest86-553422898c9b07bf068dfbb650ce2b30b84b8e8e.tar.xz memtest86-553422898c9b07bf068dfbb650ce2b30b84b8e8e.zip | |
some documentation
Diffstat (limited to 'documentation')
| -rw-r--r-- | documentation/general/APIC | 4 | ||||
| -rw-r--r-- | documentation/general/GDT | 4 | ||||
| -rw-r--r-- | documentation/general/IPI | 10 | ||||
| -rw-r--r-- | documentation/memtest86+ code/smp_c_h | 4 |
4 files changed, 21 insertions, 1 deletions
diff --git a/documentation/general/APIC b/documentation/general/APIC index 83384b7..b150f07 100644 --- a/documentation/general/APIC +++ b/documentation/general/APIC @@ -7,8 +7,10 @@ Split architecture design: local component (LAPIC) and optional I/O APIC on a sy Intel: One LAPIC in each CPU and typically one I/O APIC for each peripheral bus in the system. +Each APIC, whether a discrete chip or integrated in a CPU, has a version register containing a four-bit version number for its specific APIC implementation. For example, the 82489DX has an APIC version number of 0, while version 1 was assigned to the first generation of local APICs integrated in the Pentium 90 and 100 processors + INTEGRATED LOCAL APICS ----------------------- Manage all external interrupts for some specific processor in an SMP system. -In addition, able to accept and generate inter-processur interrupts (IPIs) between LAPICS. +In addition, able to accept and generate inter-processor interrupts (IPIs) between LAPICS. diff --git a/documentation/general/GDT b/documentation/general/GDT new file mode 100644 index 0000000..c4e0091 --- /dev/null +++ b/documentation/general/GDT @@ -0,0 +1,4 @@ +Global Descriptor Table +========================= + +Specific to IA32 architecture. diff --git a/documentation/general/IPI b/documentation/general/IPI new file mode 100644 index 0000000..5daed95 --- /dev/null +++ b/documentation/general/IPI @@ -0,0 +1,10 @@ +Inter-Processor Interrupt +============================== + +An inter-processor interrupt (IPI) is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system if the interrupting processor requires action from the other processor. Actions that might be requested include: + + - flushes of memory management unit caches, such as translation lookaside buffers, + on other processors when memory mappings are changed by one processor; + - stopping when the system is being shut down by one processor. + +On IBM PC compatible computers that use the Advanced Programmable Interrupt Controller (APIC), IPI signalling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the interrupt vector and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU. diff --git a/documentation/memtest86+ code/smp_c_h b/documentation/memtest86+ code/smp_c_h index 8ff5ce6..5d231c9 100644 --- a/documentation/memtest86+ code/smp_c_h +++ b/documentation/memtest86+ code/smp_c_h @@ -2,6 +2,10 @@ smp.h ==================================== What is the barrier structure? +FUNCTION DEFINED IN +_______________________________________________________________ ________________________________________________________________ +extern volatile apic_register_t *APIC; smp.c +apic_register_t = uint32_t[4] |