/*
* Hisilicon Ltd. HiP04 SoC
*
* Copyright (C) 2013-2014 Hisilicon Ltd.
* Copyright (C) 2013-2014 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
/* memory bus is 64-bit */
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
};
bootwrapper {
compatible = "hisilicon,hip04-bootwrapper";
boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
cluster2 {
core0 {
cpu = <&CPU8>;
};
core1 {
cpu = <&CPU9>;
};
core2 {
cpu = <&CPU10>;
};
core3 {
cpu = <&CPU11>;
};
};
cluster3 {
core0 {
cpu = <&CPU12>;
};
core1 {
cpu = <&CPU13>;
};
core2 {
cpu = <&CPU14>;
};
core3 {
cpu = <&CPU15>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <3>;
};
CPU4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x100>;
};
CPU5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x101>;
};
CPU6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x102>;
};
CPU7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x103>;
};
CPU8: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x200>;
};
CPU9: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x201>;
};
CPU10: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x202>;
};
CPU11: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x203>;
};
CPU12: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x300>;
};
CPU13: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x301>;
};
CPU14: cpu@302 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x302>;
};
CPU15: cpu@303 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x303>;
};
};
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
clk_50m: clk_50m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
clk_168m: clk_168m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <168000000>;
};
clk_375m: clk_375m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <375000000>;
};
soc {
/* It's a 32-bit SoC. */
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0 0 0xe0000000 0x10000000>;
gic: interrupt-controller@c01000 {
compatible = "hisilicon,hip04-intc";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
interrupts = <1 9 0xf04>;
reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
<0xc04000 0x2000>, <0xc06000 0x2000>;
};
sysctrl: sysctrl {
compatible = "hisilicon,sysctrl";
reg = <0x3e00000 0x00100000>;
};
fabric: fabric {
compatible = "hisilicon,hip04-fabric";
reg = <0x302a000 0x1000>;
};
dual_timer0: dual_timer@3000000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x3000000 0x1000>;
interrupts = <0 224 4>;
clocks = <&clk_50m>, <&clk_50m>;
clock-names = "apb_pclk";
};
arm-pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <0 64 4>,
<0 65 4>,
<0 66 4>,
<0 67 4>,
<0 68 4>,
<0 69 4>,
<0 70 4>,
<0 71 4>,
<0 72 4>,
<0 73 4>,
<0 74 4>,
<0 75 4>,
<0 76 4>,
<0 77 4>,
<0 78 4>,
<0 79 4>;
};
uart0: uart@4007000 {
compatible = "snps,dw-apb-uart";
reg = <0x4007000 0x1000>;
interrupts = <0 381 4>;
clocks = <&clk_168m>;
clock-names = "uartclk";
reg-shift = <2>;
status = "disabled";
};
sata0: sata@a000000 {
compatible = "hisilicon,hisi-ahci";
reg = <0xa000000 0x1000000>;
interrupts = <0 372 4>;
};
};
etb@0,e3c42000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3c42000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {
etb0_in_port: endpoint@0 {
slave-mode;
remote-endpoint = <&replicator0_out_port0>;
};
};
};
etb@0,e3c82000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3c82000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {
etb1_in_port: endpoint@0 {
slave-mode;
remote-endpoint = <&replicator1_out_port0>;
};
};
};
etb@0,e3cc2000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3cc2000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {
etb2_in_port: endpoint@0 {
slave-mode;
remote-endpoint = <&replicator2_out_port0>;
};
};
};
etb@0,e3d02000 {
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3d02000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {
etb3_in_port: endpoint@0 {
slave-mode;
remote-endpoint = <&replicator3_out_port0>;
};
};
};
tpiu@0,e3c05000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0 0xe3c05000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {
tpiu_in_port: endpoint@0 {
slave-mode;
remote-endpoint = <&funnel4_out_port0>;
};
};
};
replicator0 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator0_out_port0: endpoint {
remote-endpoint = <&etb0_in_port>;
};
};
port@1 {
reg = <1>;
replicator0_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port0>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator0_in_port0: endpoint {
slave-mode;
remote-endpoint = <&funnel0_out_port0>;
};
};
};
};
replicator1 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator1_out_port0: endpoint {
remote-endpoint = <&etb1_in_port>;
};
};
port@1 {
reg = <1>;
replicator1_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port1>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator1_in_port0: endpoint {
slave-mode;
remote-endpoint = <&funnel1_out_port0>;
};
};
};
};
replicator2 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator2_out_port0: endpoint {
remote-endpoint = <&etb2_in_port>;
};
};
port@1 {
reg = <1>;
replicator2_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port2>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator2_in_port0: endpoint {
slave-mode;
remote-endpoint = <&funnel2_out_port0>;
};
};
};
};
replicator3 {
/* non-configurable replicators don't show up on the
* AMBA bus. As such no need to add "arm,primecell".
*/
compatible = "arm,coresight-replicator";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* replicator output ports */
port@0 {
reg = <0>;
replicator3_out_port0: endpoint {
remote-endpoint = <&etb3_in_port>;
};
};
port@1 {
reg = <1>;
replicator3_out_port1: endpoint {
remote-endpoint = <&funnel4_in_port3>;
};
};
/* replicator input port */
port@2 {
reg = <0>;
replicator3_in_port0: endpoint {
slave-mode;
remote-endpoint = <&funnel3_out_port0>;
};
};
};
};
funnel@0,e3c41000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xe3c41000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel output port */
port@0 {
reg = <0>;
funnel0_out_port0: endpoint {
remote-endpoint =
<&replicator0_in_port0>;
};
};
/* funnel input ports */
port@1 {
reg = <0>;
funnel0_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ptm0_out_port>;
};
};
port@2 {
reg = <1>;
funnel0_in_port1: endpoint {
slave-mode;
remote-endpoint = <&ptm1_out_port>;
};
};
port@3 {
reg = <2>;
funnel0_in_port2: endpoint {
slave-mode;
remote-endpoint = <&ptm2_out_port>;
};
};
port@4 {
reg = <3>;
funnel0_in_port3: endpoint {
slave-mode;
remote-endpoint = <&ptm3_out_port>;
};
};
};
};
funnel@0,e3c81000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xe3c81000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel output port */
port@0 {
reg = <0>;
funnel1_out_port0: endpoint {
remote-endpoint =
<&replicator1_in_port0>;
};
};
/* funnel input ports */
port@1 {
reg = <0>;
funnel1_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ptm4_out_port>;
};
};
port@2 {
reg = <1>;
funnel1_in_port1: endpoint {
slave-mode;
remote-endpoint = <&ptm5_out_port>;
};
};
port@3 {
reg = <2>;
funnel1_in_port2: endpoint {
slave-mode;
remote-endpoint = <&ptm6_out_port>;
};
};
port@4 {
reg = <3>;
funnel1_in_port3: endpoint {
slave-mode;
remote-endpoint = <&ptm7_out_port>;
};
};
};
};
funnel@0,e3cc1000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xe3cc1000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel output port */
port@0 {
reg = <0>;
funnel2_out_port0: endpoint {
remote-endpoint =
<&replicator2_in_port0>;
};
};
/* funnel input ports */
port@1 {
reg = <0>;
funnel2_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ptm8_out_port>;
};
};
port@2 {
reg = <1>;
funnel2_in_port1: endpoint {
slave-mode;
remote-endpoint = <&ptm9_out_port>;
};
};
port@3 {
reg = <2>;
funnel2_in_port2: endpoint {
slave-mode;
remote-endpoint = <&ptm10_out_port>;
};
};
port@4 {
reg = <3>;
funnel2_in_port3: endpoint {
slave-mode;
remote-endpoint = <&ptm11_out_port>;
};
};
};
};
funnel@0,e3d01000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xe3d01000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel output port */
port@0 {
reg = <0>;
funnel3_out_port0: endpoint {
remote-endpoint =
<&replicator3_in_port0>;
};
};
/* funnel input ports */
port@1 {
reg = <0>;
funnel3_in_port0: endpoint {
slave-mode;
remote-endpoint = <&ptm12_out_port>;
};
};
port@2 {
reg = <1>;
funnel3_in_port1: endpoint {
slave-mode;
remote-endpoint = <&ptm13_out_port>;
};
};
port@3 {
reg = <2>;
funnel3_in_port2: endpoint {
slave-mode;
remote-endpoint = <&ptm14_out_port>;
};
};
port@4 {
reg = <3>;
funnel3_in_port3: endpoint {
slave-mode;
remote-endpoint = <&ptm15_out_port>;
};
};
};
};
funnel@0,e3c04000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0 0xe3c04000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* funnel output port */
port@0 {
reg = <0>;
funnel4_out_port0: endpoint {
remote-endpoint = <&tpiu_in_port>;
};
};
/* funnel input ports */
port@1 {
reg = <0>;
funnel4_in_port0: endpoint {
slave-mode;
remote-endpoint =
<&replicator0_out_port1>;
};
};
port@2 {
reg = <1>;
funnel4_in_port1: endpoint {
slave-mode;
remote-endpoint =
<&replicator1_out_port1>;
};
};
port@3 {
reg = <2>;
funnel4_in_port2: endpoint {
slave-mode;
remote-endpoint =
<&replicator2_out_port1>;
};
};
port@4 {
reg = <3>;
funnel4_in_port3: endpoint {
slave-mode;
remote-endpoint =
<&replicator3_out_port1>;
};
};
};
};
ptm@0,e3c7c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7c000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
port {
ptm0_out_port: endpoint {
remote-endpoint = <&funnel0_in_port0>;
};
};
};
ptm@0,e3c7d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7d000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
port {
ptm1_out_port: endpoint {
remote-endpoint = <&funnel0_in_port1>;
};
};
};
ptm@0,e3c7e000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7e000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
port {
ptm2_out_port: endpoint {
remote-endpoint = <&funnel0_in_port2>;
};
};
};
ptm@0,e3c7f000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3c7f000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
port {
ptm3_out_port: endpoint {
remote-endpoint = <&funnel0_in_port3>;
};
};
};
ptm@0,e3cbc000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbc000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU4>;
port {
ptm4_out_port: endpoint {
remote-endpoint = <&funnel1_in_port0>;
};
};
};
ptm@0,e3cbd000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbd000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU5>;
port {
ptm5_out_port: endpoint {
remote-endpoint = <&funnel1_in_port1>;
};
};
};
ptm@0,e3cbe000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbe000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU6>;
port {
ptm6_out_port: endpoint {
remote-endpoint = <&funnel1_in_port2>;
};
};
};
ptm@0,e3cbf000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cbf000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU7>;
port {
ptm7_out_port: endpoint {
remote-endpoint = <&funnel1_in_port3>;
};
};
};
ptm@0,e3cfc000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cfc000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU8>;
port {
ptm8_out_port: endpoint {
remote-endpoint = <&funnel2_in_port0>;
};
};
};
ptm@0,e3cfd000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cfd000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU9>;
port {
ptm9_out_port: endpoint {
remote-endpoint = <&funnel2_in_port1>;
};
};
};
ptm@0,e3cfe000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cfe000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU10>;
port {
ptm10_out_port: endpoint {
remote-endpoint = <&funnel2_in_port2>;
};
};
};
ptm@0,e3cff000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3cff000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU11>;
port {
ptm11_out_port: endpoint {
remote-endpoint = <&funnel2_in_port3>;
};
};
};
ptm@0,e3d3c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3c000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU12>;
port {
ptm12_out_port: endpoint {
remote-endpoint = <&funnel3_in_port0>;
};
};
};
ptm@0,e3d3d000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3d000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU13>;
port {
ptm13_out_port: endpoint {
remote-endpoint = <&funnel3_in_port1>;
};
};
};
ptm@0,e3d3e000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3e000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU14>;
port {
ptm14_out_port: endpoint {
remote-endpoint = <&funnel3_in_port2>;
};
};
};
ptm@0,e3d3f000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0 0xe3d3f000 0 0x1000>;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
cpu = <&CPU15>;
port {
ptm15_out_port: endpoint {
remote-endpoint = <&funnel3_in_port3>;
};
};
};
};
