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/*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx1.dtsi"
/ {
model = "Freescale MX1 ADS";
compatible = "fsl,imx1ads", "fsl,imx1";
chosen {
stdout-path = &uart1;
};
memory@8000000 {
device_type = "memory";
reg = <0x08000000 0x04000000>;
};
};
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>;
cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c>;
status = "okay";
extgpio0: pcf8575@22 {
compatible = "nxp,pcf8575";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
extgpio1: pcf8575@24 {
compatible = "nxp,pcf8575";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
nor: nor@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <4>;
fsl,weim-cs-timing = <0x00003e00 0x00000801>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&iomuxc {
imx1-ads {
pinctrl_cspi1: cspi1grp {
fsl,pins = <
MX1_PAD_SPI1_MISO__SPI1_MISO 0x0
MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0
MX1_PAD_SPI1_RDY__SPI1_RDY 0x0
MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0
MX1_PAD_SPI1_SS__GPIO3_15 0x0
>;
};
pinctrl_i2c: i2cgrp {
fsl,pins = <
MX1_PAD_I2C_SCL__I2C_SCL 0x0
MX1_PAD_I2C_SDA__I2C_SDA 0x0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX1_PAD_UART1_TXD__UART1_TXD 0x0
MX1_PAD_UART1_RXD__UART1_RXD 0x0
MX1_PAD_UART1_CTS__UART1_CTS 0x0
MX1_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX1_PAD_UART2_TXD__UART2_TXD 0x0
MX1_PAD_UART2_RXD__UART2_RXD 0x0
MX1_PAD_UART2_CTS__UART2_CTS 0x0
MX1_PAD_UART2_RTS__UART2_RTS 0x0
>;
};
pinctrl_weim: weimgrp {
fsl,pins = <
MX1_PAD_A0__A0 0x0
MX1_PAD_A16__A16 0x0
MX1_PAD_A17__A17 0x0
MX1_PAD_A18__A18 0x0
MX1_PAD_A19__A19 0x0
MX1_PAD_A20__A20 0x0
MX1_PAD_A21__A21 0x0
MX1_PAD_A22__A22 0x0
MX1_PAD_A23__A23 0x0
MX1_PAD_A24__A24 0x0
MX1_PAD_BCLK__BCLK 0x0
MX1_PAD_CS4__CS4 0x0
MX1_PAD_DTACK__DTACK 0x0
MX1_PAD_ECB__ECB 0x0
MX1_PAD_LBA__LBA 0x0
>;
};
};
};
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