/*
* ox820.dtsi - Device tree file for Oxford Semiconductor OX820 SoC
*
* Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
*
* Licensed under GPLv2 or later
*/
/include/ "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/oxsemi,ox820.h>
#include <dt-bindings/reset/oxsemi,ox820.h>
/ {
compatible = "oxsemi,ox820";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "oxsemi,ox820-smp";
cpu@0 {
device_type = "cpu";
compatible = "arm,arm11mpcore";
clocks = <&armclk>;
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,arm11mpcore";
clocks = <&armclk>;
reg = <1>;
};
};
memory {
/* Max 512MB @ 0x60000000 */
reg = <0x60000000 0x20000000>;
};
clocks {
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
gmacclk: gmacclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
sysclk: sysclk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <4>;
clock-mult = <1>;
clocks = <&osc>;
};
plla: plla {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <850000000>;
};
armclk: armclk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
clocks = <&plla>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
interrupt-parent = <&gic>;
nandc: nand-controller@41000000 {
compatible = "oxsemi,ox820-nand";
reg = <0x41000000 0x100000>;
clocks = <&stdclk CLK_820_NAND>;
resets = <&reset RESET_NAND>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
etha: ethernet@40400000 {
compatible = "oxsemi,ox820-dwmac", "snps,dwmac";
reg = <0x40400000 0x2000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
mac-address = [000000000000]; /* Filled in by U-Boot */
phy-mode = "rgmii";
clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
clock-names = "gmac", "stmmaceth";
resets = <&reset RESET_MAC>;
/* Regmap for sys registers */
oxsemi,sys-ctrl = <&sys>;
status = "disabled";
};
apb-bridge@44000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0x44000000 0x1000000>;
pinctrl: pinctrl {
compatible = "oxsemi,ox820-pinctrl";
/* Regmap for sys registers */
oxsemi,sys-ctrl = <&sys>;
pinctrl_uart0: uart0 {
uart0 {
pins = "gpio30", "gpio31";
function = "fct5";
};
};
pinctrl_uart0_modem: uart0_modem {
uart0_modem_a {
pins = "gpio24", "gpio24", "gpio26", "gpio27";
function = "fct4";
};
uart0_modem_b {
pins = "gpio28", "gpio29";
function = "fct5";
};
};
pinctrl_uart1: uart1 {
uart1 {
pins = "gpio7", "gpio8";
function = "fct4";
};
};
pinctrl_uart1_modem: uart1_modem {
uart1_modem {
pins = "gpio5", "gpio6", "gpio40", "gpio41", "gpio42", "gpio43";
function = "fct4";
};
};
pinctrl_etha_mdio: etha_mdio {
etha_mdio {
pins = "gpio3", "gpio4";
function = "fct1";
};
};
pinctrl_nand: nand {
nand {
pins = "gpio12", "gpio13", "gpio14", "gpio15",
"gpio16", "gpio17", "gpio18", "gpio19",
"gpio20", "gpio21", "gpio22", "gpio23",
"gpio24";
function = "fct1";
};
};
};
gpio0: gpio@0 {
compatible = "oxsemi,ox820-gpio";
reg = <0x000000 0x100000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
ngpios = <32>;
oxsemi,gpio-bank = <0>;
gpio-ranges = <&pinctrl 0 0 32>;
};
gpio1: gpio@100000 {
compatible = "oxsemi,ox820-gpio";
reg = <0x100000 0x100000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
ngpios = <18>;
oxsemi,gpio-bank = <1>;
gpio-ranges = <&pinctrl 0 32 18>;
};
uart0: serial@200000 {
compatible = "ns16550a";
reg = <0x200000 0x100000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <0>;
fifo-size = <16>;
reg-io-width = <1>;
current-speed = <115200>;
no-loopback-test;
status = "disabled";
clocks = <&sysclk>;
resets = <&reset RESET_UART1>;
};
uart1: serial@300000 {
compatible = "ns16550a";
reg = <0x200000 0x100000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <0>;
fifo-size = <16>;
reg-io-width = <1>;
current-speed = <115200>;
no-loopback-test;
status = "disabled";
clocks = <&sysclk>;
resets = <&reset RESET_UART2>;
};
rps@400000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0x400000 0x100000>;
intc: interrupt-controller@0 {
compatible = "oxsemi,ox820-rps-irq", "oxsemi,ox810se-rps-irq";
interrupt-controller;
reg = <0 0x200>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
valid-mask = <0xFFFFFFFF>;
clear-mask = <0>;
};
timer0: timer@200 {
compatible = "oxsemi,ox820-rps-timer";
reg = <0x200 0x40>;
clocks = <&sysclk>;
interrupt-parent = <&intc>;
interrupts = <4>;
};
};
sys: sys-ctrl@e00000 {
compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
reg = <0xe00000 0x200000>;
reset: reset-controller {
compatible = "oxsemi,ox820-reset", "oxsemi,ox810se-reset";
#reset-cells = <1>;
};
stdclk: stdclk {
compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
#clock-cells = <1>;
};
};
};
apb-bridge@47000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0x47000000 0x1000000>;
scu: scu@0 {
compatible = "arm,arm11mp-scu";
reg = <0x0 0x100>;
};
local-timer@600 {
compatible = "arm,arm11mp-twd-timer";
reg = <0x600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&armclk>;
};
gic: gic@1000 {
compatible = "arm,arm11mp-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x1000 0x1000>,
<0x100 0x500>;
};
};
};
};
