path: root/arch/arm/boot/dts/ste-u300.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree for the ST-Ericsson U300 Machine and SoC
 */

/dts-v1/;
/include/ "skeleton.dtsi"

/ {
	model = "ST-Ericsson U300";
	compatible = "stericsson,u300";
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
		bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
	};

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
        };

	memory {
		reg = <0x48000000 0x03c00000>;
	};

	s365 {
		compatible = "stericsson,s365";
		vana15-supply = <&ab3100_ldo_d_reg>;
		syscon = <&syscon>;
	};

	syscon: syscon@c0011000 {
		compatible = "stericsson,u300-syscon", "syscon";
		reg = <0xc0011000 0x1000>;
		clk32: app_32_clk@32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};
		pll13: pll13@13M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <13000000>;
		};
		/* Slow bridge clocks under PLL13 */
		slow_clk: slow_clk@13M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <0>; /* Slow */
			clock-id = <0>;
			clocks = <&pll13>;
		};
		uart0_clk: uart0_clk@13M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <0>; /* Slow */
			clock-id = <1>;
			clocks = <&slow_clk>;
		};
		gpio_clk: gpio_clk@13M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <0>; /* Slow */
			clock-id = <4>;
			clocks = <&slow_clk>;
		};
		rtc_clk: rtc_clk@13M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <0>; /* Slow */
			clock-id = <6>;
			clocks = <&slow_clk>;
		};
		apptimer_clk: app_tmr_clk@13M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <0>; /* Slow */
			clock-id = <7>;
			clocks = <&slow_clk>;
		};
		acc_tmr_clk@13M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <0>; /* Slow */
			clock-id = <8>;
			clocks = <&slow_clk>;
		};
		pll208: pll208@208M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <208000000>;
		};
		app208: app_208_clk@208M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&pll208>;
		};
		cpu_clk@208M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <3>;
			clocks = <&app208>;
		};
		app104: app_104_clk@104M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <2>;
			clock-mult = <1>;
			clocks = <&pll208>;
		};
		semi_clk@104M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <9>;
			clocks = <&app104>;
		};
		app52: app_52_clk@52M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <4>;
			clock-mult = <1>;
			clocks = <&pll208>;
		};
		/* AHB subsystem clocks */
		ahb_clk: ahb_subsys_clk@52M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <10>;
			clocks = <&app52>;
		};
		intcon_clk@52M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <12>;
			clocks = <&ahb_clk>;
		};
		emif_clk@52M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <5>;
			clocks = <&ahb_clk>;
		};
		dmac_clk: dmac_clk@52M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <4>;
			clocks = <&app52>;
		};
		fsmc_clk: fsmc_clk@52M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <6>;
			clocks = <&app52>;
		};
		xgam_clk: xgam_clk@52M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <2>; /* Rest */
			clock-id = <8>;
			clocks = <&app52>;
		};
		app26: app_26_clk@26M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <2>;
			clock-mult = <1>;
			clocks = <&app52>;
		};
		/* Fast bridge  clocks */
		fast_clk: fast_clk@26M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <1>; /* Fast */
			clock-id = <0>;
			clocks = <&app26>;
		};
		i2c0_clk: i2c0_clk@26M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <1>; /* Fast */
			clock-id = <1>;
			clocks = <&fast_clk>;
		};
		i2c1_clk: i2c1_clk@26M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <1>; /* Fast */
			clock-id = <2>;
			clocks = <&fast_clk>;
		};
		mmc_pclk: mmc_p_clk@26M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <1>; /* Fast */
			clock-id = <5>;
			clocks = <&fast_clk>;
		};
		mmc_mclk: mmc_mclk {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-mclk";
			clocks = <&mmc_pclk>;
		};
		spi_clk: spi_p_clk@26M {
			#clock-cells = <0>;
			compatible = "stericsson,u300-syscon-clk";
			clock-type = <1>; /* Fast */
			clock-id = <6>;
			clocks = <&fast_clk>;
		};
	};

	timer: timer@c0014000 {
		compatible = "stericsson,u300-apptimer";
		reg = <0xc0014000 0x1000>;
		interrupt-parent = <&vica>;
		interrupts = <24 25 26 27>;
		clocks = <&apptimer_clk>;
	};

	gpio: gpio@c0016000 {
		compatible = "stericsson,gpio-coh901";
		reg = <0xc0016000 0x1000>;
		interrupt-parent = <&vicb>;
		interrupts = <0 1 2 18 21 22 23>;
		clocks = <&gpio_clk>;
		interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
				"gpio4", "gpio5", "gpio6";
		interrupt-controller;
		#interrupt-cells = <2>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pinctrl: pinctrl@c0011000 {
		compatible = "stericsson,pinctrl-u300";
		reg = <0xc0011000 0x1000>;
	};

	watchdog: watchdog@c0012000 {
		compatible = "stericsson,coh901327";
		reg = <0xc0012000 0x1000>;
		interrupt-parent = <&vicb>;
		interrupts = <3>;
		clocks = <&clk32>;
	};

	rtc: rtc@c0017000 {
		compatible = "stericsson,coh901331";
		reg = <0xc0017000 0x1000>;
		interrupt-parent = <&vicb>;
		interrupts = <10>;
		clocks = <&rtc_clk>;
	};

	dmac: dma-controller@c00020000 {
		compatible = "stericsson,coh901318";
		reg = <0xc0020000 0x1000>;
		interrupt-parent = <&vica>;
		interrupts = <2>;
		#dma-cells = <1>;
		dma-channels = <40>;
		clocks = <&dmac_clk>;
	};

	/* A NAND flash of 128 MiB */
	fsmc: flash@40000000 {
		compatible = "stericsson,fsmc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x9f800000 0x1000>,	/* FSMC Register*/
			<0x80000000 0x4000>,	/* NAND Base DATA */
			<0x80020000 0x4000>,	/* NAND Base ADDR */
			<0x80010000 0x4000>;	/* NAND Base CMD */
		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
		nand-skip-bbtscan;
		clocks = <&fsmc_clk>;

		partition@0 {
		label = "boot records";
			reg = <0x0 0x20000>;
		};
		partition@20000 {
			label = "free";
			reg = <0x20000 0x7e0000>;
		};
		partition@800000 {
			label = "platform";
			reg = <0x800000 0xf800000>;
		};
	};

	i2c0: i2c@c0004000 {
		compatible = "st,ddci2c";
		reg = <0xc0004000 0x1000>;
		interrupt-parent = <&vicb>;
		interrupts = <8>;
		clocks = <&i2c0_clk>;
		#address-cells = <1>;
		#size-cells = <0>;
		ab3100: ab3100@48 {
			compatible = "stericsson,ab3100";
			reg = <0x48>;
			interrupt-parent = <&vica>;
			interrupts = <0>; /* EXT0 IRQ */
			ab3100-regulators {
				compatible = "stericsson,ab3100-regulators";
				ab3100_ldo_a_reg: ab3100_ldo_a {
					startup-delay-us = <200>;
					regulator-always-on;
					regulator-boot-on;
				};
				ab3100_ldo_c_reg: ab3100_ldo_c {
					startup-delay-us = <200>;
				};
				ab3100_ldo_d_reg: ab3100_ldo_d {
					startup-delay-us = <200>;
				};
				ab3100_ldo_e_reg: ab3100_ldo_e {
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					startup-delay-us = <200>;
					regulator-always-on;
					regulator-boot-on;
				};
				ab3100_ldo_f_reg: ab3100_ldo_f {
					regulator-min-microvolt = <2500000>;
					regulator-max-microvolt = <2500000>;
					startup-delay-us = <600>;
					regulator-always-on;
					regulator-boot-on;
				};
				ab3100_ldo_g_reg: ab3100_ldo_g {
					regulator-min-microvolt = <1500000>;
					regulator-max-microvolt = <2850000>;
					startup-delay-us = <400>;
				};
				ab3100_ldo_h_reg: ab3100_ldo_h {
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <2750000>;
					startup-delay-us = <200>;
				};
				ab3100_ldo_k_reg: ab3100_ldo_k {
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <2750000>;
					startup-delay-us = <200>;
				};
				ab3100_ext_reg: ab3100_ext {
				};
				ab3100_buck_reg: ab3100_buck {
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1800000>;
					startup-delay-us = <1000>;
					regulator-always-on;
					regulator-boot-on;
				};
			};
		};
	};

	i2c1: i2c@c0005000 {
		compatible = "st,ddci2c";
		reg = <0xc0005000 0x1000>;
		interrupt-parent = <&vicb>;
		interrupts = <9>;
		clocks = <&i2c1_clk>;
		#address-cells = <1>;
		#size-cells = <0>;
		fwcam0: fwcam@10 {
			reg = <0x10>;
		};
		fwcam1: fwcam@5d {
			reg = <0x5d>;
		};
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vica: interrupt-controller@a0001000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0xa0001000 0x20>;
		};

		vicb: interrupt-controller@a0002000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0xa0002000 0x20>;
		};

		uart0: serial@c0013000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xc0013000 0x1000>;
			interrupt-parent = <&vica>;
			interrupts = <22>;
			clocks = <&uart0_clk>, <&uart0_clk>;
			clock-names = "apb_pclk", "uart0_clk";
			dmas = <&dmac 17 &dmac 18>;
			dma-names = "tx", "rx";
		};

		uart1: serial@c0007000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0xc0007000 0x1000>;
			interrupt-parent = <&vicb>;
			interrupts = <20>;
			dmas = <&dmac 38 &dmac 39>;
			dma-names = "tx", "rx";
		};

		mmcsd: mmcsd@c0001000 {
			compatible = "arm,pl18x", "arm,primecell";
			reg = <0xc0001000 0x1000>;
			interrupt-parent = <&vicb>;
			interrupts = <6 7>;
			clocks = <&mmc_pclk>, <&mmc_mclk>;
			clock-names = "apb_pclk", "mclk";
			max-frequency = <24000000>;
			bus-width = <4>; // SD-card slot
			cap-mmc-highspeed;
			cap-sd-highspeed;
			cd-gpios = <&gpio 12 0x4>;
			cd-inverted;
			vmmc-supply = <&ab3100_ldo_g_reg>;
			dmas = <&dmac 14>;
			dma-names = "rx";
		};

		spi: ssp@c0006000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0xc0006000 0x1000>;
			interrupt-parent = <&vica>;
			interrupts = <23>;
			clocks = <&spi_clk>, <&spi_clk>;
			clock-names = "SSPCLK", "apb_pclk";
			dmas = <&dmac 27 &dmac 28>;
			dma-names = "tx", "rx";
			num-cs = <3>;
			#address-cells = <1>;
			#size-cells = <0>;
			spi-dummy@1 {
				compatible = "arm,pl022-dummy";
				reg = <1>;
				spi-max-frequency = <20000000>;
			};
		};
	};
};