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path: root/arch/arm/boot/dts/tegra20-harmony.dts
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// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/input/input.h>
#include "tegra20.dtsi"

/ {
	model = "NVIDIA Tegra20 Harmony evaluation board";
	compatible = "nvidia,harmony", "nvidia,tegra20";

	aliases {
		rtc0 = "/i2c@7000d000/tps6586x@34";
		rtc1 = "/rtc@7000e000";
		serial0 = &uartd;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		reg = <0x00000000 0x40000000>;
	};

	host1x@50000000 {
		dc@54200000 {
			rgb {
				status = "okay";

				nvidia,panel = <&panel>;
			};
		};

		hdmi@54280000 {
			status = "okay";

			hdmi-supply = <&vdd_5v0_hdmi>;
			vdd-supply = <&hdmi_vdd_reg>;
			pll-supply = <&hdmi_pll_reg>;

			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
				GPIO_ACTIVE_HIGH>;
		};
	};

	pinmux@70000014 {
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			ata {
				nvidia,pins = "ata";
				nvidia,function = "ide";
			};
			atb {
				nvidia,pins = "atb", "gma", "gme";
				nvidia,function = "sdio4";
			};
			atc {
				nvidia,pins = "atc";
				nvidia,function = "nand";
			};
			atd {
				nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
					"spia", "spib", "spic";
				nvidia,function = "gmi";
			};
			cdev1 {
				nvidia,pins = "cdev1";
				nvidia,function = "plla_out";
			};
			cdev2 {
				nvidia,pins = "cdev2";
				nvidia,function = "pllp_out4";
			};
			crtp {
				nvidia,pins = "crtp";
				nvidia,function = "crt";
			};
			csus {
				nvidia,pins = "csus";
				nvidia,function = "vi_sensor_clk";
			};
			dap1 {
				nvidia,pins = "dap1";
				nvidia,function = "dap1";
			};
			dap2 {
				nvidia,pins = "dap2";
				nvidia,function = "dap2";
			};
			dap3 {
				nvidia,pins = "dap3";
				nvidia,function = "dap3";
			};
			dap4 {
				nvidia,pins = "dap4";
				nvidia,function = "dap4";
			};
			ddc {
				nvidia,pins = "ddc";
				nvidia,function = "i2c2";
			};
			dta {
				nvidia,pins = "dta", "dtd";
				nvidia,function = "sdio2";
			};
			dtb {
				nvidia,pins = "dtb", "dtc", "dte";
				nvidia,function = "rsvd1";
			};
			dtf {
				nvidia,pins = "dtf";
				nvidia,function = "i2c3";
			};
			gmc {
				nvidia,pins = "gmc";
				nvidia,function = "uartd";
			};
			gpu7 {
				nvidia,pins = "gpu7";
				nvidia,function = "rtck";
			};
			gpv {
				nvidia,pins = "gpv", "slxa", "slxk";
				nvidia,function = "pcie";
			};
			hdint {
				nvidia,pins = "hdint", "pta";
				nvidia,function = "hdmi";
			};
			i2cp {
				nvidia,pins = "i2cp";
				nvidia,function = "i2cp";
			};
			irrx {
				nvidia,pins = "irrx", "irtx";
				nvidia,function = "uarta";
			};
			kbca {
				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
					"kbce", "kbcf";
				nvidia,function = "kbc";
			};
			lcsn {
				nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
					"ld3", "ld4", "ld5", "ld6", "ld7",
					"ld8", "ld9", "ld10", "ld11", "ld12",
					"ld13", "ld14", "ld15", "ld16", "ld17",
					"ldc", "ldi", "lhp0", "lhp1", "lhp2",
					"lhs", "lm0", "lm1", "lpp", "lpw0",
					"lpw1", "lpw2", "lsc0", "lsc1", "lsck",
					"lsda", "lsdi", "lspi", "lvp0", "lvp1",
					"lvs";
				nvidia,function = "displaya";
			};
			owc {
				nvidia,pins = "owc", "spdi", "spdo", "uac";
				nvidia,function = "rsvd2";
			};
			pmc {
				nvidia,pins = "pmc";
				nvidia,function = "pwr_on";
			};
			rm {
				nvidia,pins = "rm";
				nvidia,function = "i2c1";
			};
			sdb {
				nvidia,pins = "sdb", "sdc", "sdd";
				nvidia,function = "pwm";
			};
			sdio1 {
				nvidia,pins = "sdio1";
				nvidia,function = "sdio1";
			};
			slxc {
				nvidia,pins = "slxc", "slxd";
				nvidia,function = "spdif";
			};
			spid {
				nvidia,pins = "spid", "spie", "spif";
				nvidia,function = "spi1";
			};
			spig {
				nvidia,pins = "spig", "spih";
				nvidia,function = "spi2_alt";
			};
			uaa {
				nvidia,pins = "uaa", "uab", "uda";
				nvidia,function = "ulpi";
			};
			uad {
				nvidia,pins = "uad";
				nvidia,function = "irda";
			};
			uca {
				nvidia,pins = "uca", "ucb";
				nvidia,function = "uartc";
			};
			conf_ata {
				nvidia,pins = "ata", "atb", "atc", "atd", "ate",
					"cdev1", "cdev2", "dap1", "dtb", "gma",
					"gmb", "gmc", "gmd", "gme", "gpu7",
					"gpv", "i2cp", "pta", "rm", "slxa",
					"slxk", "spia", "spib", "uac";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			conf_ck32 {
				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
			};
			conf_csus {
				nvidia,pins = "csus", "spid", "spif";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_crtp {
				nvidia,pins = "crtp", "dap2", "dap3", "dap4",
					"dtc", "dte", "dtf", "gpu", "sdio1",
					"slxc", "slxd", "spdi", "spdo", "spig",
					"uda";
				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_ddc {
				nvidia,pins = "ddc", "dta", "dtd", "kbca",
					"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
					"sdc";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			conf_hdint {
				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
					"lpw1", "lsc1", "lsck", "lsda", "lsdi",
					"lvp0", "owc", "sdb";
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_irrx {
				nvidia,pins = "irrx", "irtx", "sdd", "spic",
					"spie", "spih", "uaa", "uab", "uad",
					"uca", "ucb";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
				nvidia,tristate = <TEGRA_PIN_ENABLE>;
			};
			conf_lc {
				nvidia,pins = "lc", "ls";
				nvidia,pull = <TEGRA_PIN_PULL_UP>;
			};
			conf_ld0 {
				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
					"ld5", "ld6", "ld7", "ld8", "ld9",
					"ld10", "ld11", "ld12", "ld13", "ld14",
					"ld15", "ld16", "ld17", "ldi", "lhp0",
					"lhp1", "lhp2", "lhs", "lm0", "lpp",
					"lpw0", "lpw2", "lsc0", "lspi", "lvp1",
					"lvs", "pmc";
				nvidia,tristate = <TEGRA_PIN_DISABLE>;
			};
			conf_ld17_0 {
				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
					"ld23_22";
				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
			};
		};
	};

	i2s@70002800 {
		status = "okay";
	};

	serial@70006300 {
		status = "okay";
	};

	pwm: pwm@7000a000 {
		status = "okay";
	};

	i2c@7000c000 {
		status = "okay";
		clock-frequency = <400000>;

		wm8903: wm8903@1a {
			compatible = "wlf,wm8903";
			reg = <0x1a>;
			interrupt-parent = <&gpio>;
			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;
			#gpio-cells = <2>;

			micdet-cfg = <0>;
			micdet-delay = <100>;
			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
		};
	};

	hdmi_ddc: i2c@7000c400 {
		status = "okay";
		clock-frequency = <100000>;
	};

	i2c@7000c500 {
		status = "okay";
		clock-frequency = <400000>;
	};

	i2c@7000d000 {
		status = "okay";
		clock-frequency = <400000>;

		pmic: tps6586x@34 {
			compatible = "ti,tps6586x";
			reg = <0x34>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

			ti,system-power-controller;

			#gpio-cells = <2>;
			gpio-controller;

			sys-supply = <&vdd_5v0_reg>;
			vin-sm0-supply = <&sys_reg>;
			vin-sm1-supply = <&sys_reg>;
			vin-sm2-supply = <&sys_reg>;
			vinldo01-supply = <&sm2_reg>;
			vinldo23-supply = <&sm2_reg>;
			vinldo4-supply = <&sm2_reg>;
			vinldo678-supply = <&sm2_reg>;
			vinldo9-supply = <&sm2_reg>;

			regulators {
				sys_reg: sys {
					regulator-name = "vdd_sys";
					regulator-always-on;
				};

				sm0 {
					regulator-name = "vdd_sm0,vdd_core";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				sm1 {
					regulator-name = "vdd_sm1,vdd_cpu";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
				};

				sm2_reg: sm2 {
					regulator-name = "vdd_sm2,vin_ldo*";
					regulator-min-microvolt = <3700000>;
					regulator-max-microvolt = <3700000>;
					regulator-always-on;
				};

				pci_clk_reg: ldo0 {
					regulator-name = "vdd_ldo0,vddio_pex_clk";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				ldo1 {
					regulator-name = "vdd_ldo1,avdd_pll*";
					regulator-min-microvolt = <1100000>;
					regulator-max-microvolt = <1100000>;
					regulator-always-on;
				};

				ldo2 {
					regulator-name = "vdd_ldo2,vdd_rtc";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
				};

				ldo3 {
					regulator-name = "vdd_ldo3,avdd_usb*";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				ldo4 {
					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo5 {
					regulator-name = "vdd_ldo5,vcore_mmc";
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					regulator-always-on;
				};

				ldo6 {
					regulator-name = "vdd_ldo6,avdd_vdac";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};

				hdmi_vdd_reg: ldo7 {
					regulator-name = "vdd_ldo7,avdd_hdmi";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
				};

				hdmi_pll_reg: ldo8 {
					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
				};

				ldo9 {
					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
					regulator-min-microvolt = <2850000>;
					regulator-max-microvolt = <2850000>;
					regulator-always-on;
				};

				ldo_rtc {
					regulator-name = "vdd_rtc_out,vdd_cell";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};
			};
		};

		temperature-sensor@4c {
			compatible = "adi,adt7461";
			reg = <0x4c>;
		};
	};

	kbc@7000e200 {
		status = "okay";
		nvidia,debounce-delay-ms = <2>;
		nvidia,repeat-delay-ms = <160>;
		nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
		nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
				MATRIX_KEY(0x00, 0x03, KEY_S)
				MATRIX_KEY(0x00, 0x04, KEY_A)
				MATRIX_KEY(0x00, 0x05, KEY_Z)
				MATRIX_KEY(0x00, 0x07, KEY_FN)
				MATRIX_KEY(0x01, 0x07, KEY_MENU)
				MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
				MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
				MATRIX_KEY(0x03, 0x00, KEY_5)
				MATRIX_KEY(0x03, 0x01, KEY_4)
				MATRIX_KEY(0x03, 0x02, KEY_R)
				MATRIX_KEY(0x03, 0x03, KEY_E)
				MATRIX_KEY(0x03, 0x04, KEY_F)
				MATRIX_KEY(0x03, 0x05, KEY_D)
				MATRIX_KEY(0x03, 0x06, KEY_X)
				MATRIX_KEY(0x04, 0x00, KEY_7)
				MATRIX_KEY(0x04, 0x01, KEY_6)
				MATRIX_KEY(0x04, 0x02, KEY_T)
				MATRIX_KEY(0x04, 0x03, KEY_H)
				MATRIX_KEY(0x04, 0x04, KEY_G)
				MATRIX_KEY(0x04, 0x05, KEY_V)
				MATRIX_KEY(0x04, 0x06, KEY_C)
				MATRIX_KEY(0x04, 0x07, KEY_SPACE)
				MATRIX_KEY(0x05, 0x00, KEY_9)
				MATRIX_KEY(0x05, 0x01, KEY_8)
				MATRIX_KEY(0x05, 0x02, KEY_U)
				MATRIX_KEY(0x05, 0x03, KEY_Y)
				MATRIX_KEY(0x05, 0x04, KEY_J)
				MATRIX_KEY(0x05, 0x05, KEY_N)
				MATRIX_KEY(0x05, 0x06, KEY_B)
				MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
				MATRIX_KEY(0x06, 0x00, KEY_MINUS)
				MATRIX_KEY(0x06, 0x01, KEY_0)
				MATRIX_KEY(0x06, 0x02, KEY_O)
				MATRIX_KEY(0x06, 0x03, KEY_I)
				MATRIX_KEY(0x06, 0x04, KEY_L)
				MATRIX_KEY(0x06, 0x05, KEY_K)
				MATRIX_KEY(0x06, 0x06, KEY_COMMA)
				MATRIX_KEY(0x06, 0x07, KEY_M)
				MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
				MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
				MATRIX_KEY(0x07, 0x03, KEY_ENTER)
				MATRIX_KEY(0x07, 0x07, KEY_MENU)
				MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
				MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
				MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
				MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
				MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
				MATRIX_KEY(0x0B, 0x01, KEY_P)
				MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
				MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
				MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
				MATRIX_KEY(0x0B, 0x05, KEY_DOT)
				MATRIX_KEY(0x0C, 0x00, KEY_F10)
				MATRIX_KEY(0x0C, 0x01, KEY_F9)
				MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
				MATRIX_KEY(0x0C, 0x03, KEY_3)
				MATRIX_KEY(0x0C, 0x04, KEY_2)
				MATRIX_KEY(0x0C, 0x05, KEY_UP)
				MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
				MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
				MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
				MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
				MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
				MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
				MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
				MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
				MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
				MATRIX_KEY(0x0E, 0x00, KEY_F11)
				MATRIX_KEY(0x0E, 0x01, KEY_F12)
				MATRIX_KEY(0x0E, 0x02, KEY_F8)
				MATRIX_KEY(0x0E, 0x03, KEY_Q)
				MATRIX_KEY(0x0E, 0x04, KEY_F4)
				MATRIX_KEY(0x0E, 0x05, KEY_F3)
				MATRIX_KEY(0x0E, 0x06, KEY_1)
				MATRIX_KEY(0x0E, 0x07, KEY_F7)
				MATRIX_KEY(0x0F, 0x00, KEY_ESC)
				MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
				MATRIX_KEY(0x0F, 0x02, KEY_F5)
				MATRIX_KEY(0x0F, 0x03, KEY_TAB)
				MATRIX_KEY(0x0F, 0x04, KEY_F1)
				MATRIX_KEY(0x0F, 0x05, KEY_F2)
				MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
				MATRIX_KEY(0x0F, 0x07, KEY_F6)
				MATRIX_KEY(0x14, 0x00, KEY_KP7)
				MATRIX_KEY(0x15, 0x00, KEY_KP9)
				MATRIX_KEY(0x15, 0x01, KEY_KP8)
				MATRIX_KEY(0x15, 0x02, KEY_KP4)
				MATRIX_KEY(0x15, 0x04, KEY_KP1)
				MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
				MATRIX_KEY(0x16, 0x02, KEY_KP6)
				MATRIX_KEY(0x16, 0x03, KEY_KP5)
				MATRIX_KEY(0x16, 0x04, KEY_KP3)
				MATRIX_KEY(0x16, 0x05, KEY_KP2)
				MATRIX_KEY(0x16, 0x07, KEY_KP0)
				MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
				MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
				MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
				MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
				MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
				MATRIX_KEY(0x1D, 0x03, KEY_HOME)
				MATRIX_KEY(0x1D, 0x04, KEY_END)
				MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
				MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
				MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
				MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
				MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
				MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
				MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
	};

	pmc@7000e400 {
		nvidia,invert-interrupt;
		nvidia,suspend-mode = <1>;
		nvidia,cpu-pwr-good-time = <5000>;
		nvidia,cpu-pwr-off-time = <5000>;
		nvidia,core-pwr-good-time = <3845 3845>;
		nvidia,core-pwr-off-time = <3875>;
		nvidia,sys-clock-req-active-high;
	};

	pcie@80003000 {
		status = "okay";

		avdd-pex-supply = <&pci_vdd_reg>;
		vdd-pex-supply = <&pci_vdd_reg>;
		avdd-pex-pll-supply = <&pci_vdd_reg>;
		avdd-plle-supply = <&pci_vdd_reg>;
		vddio-pex-clk-supply = <&pci_clk_reg>;

		pci@1,0 {
			status = "okay";
		};

		pci@2,0 {
			status = "okay";
		};
	};

	usb@c5000000 {
		status = "okay";
	};

	usb-phy@c5000000 {
		status = "okay";
	};

	usb@c5004000 {
		status = "okay";
		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
			GPIO_ACTIVE_LOW>;
	};

	usb-phy@c5004000 {
		status = "okay";
		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
			GPIO_ACTIVE_LOW>;
	};

	usb@c5008000 {
		status = "okay";
	};

	usb-phy@c5008000 {
		status = "okay";
	};

	sdhci@c8000200 {
		status = "okay";
		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
		power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
		bus-width = <4>;
	};

	sdhci@c8000600 {
		status = "okay";
		cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
		wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
		bus-width = <8>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";

		enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
		power-supply = <&vdd_bl_reg>;
		pwms = <&pwm 0 5000000>;

		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <6>;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clock@0 {
			compatible = "fixed-clock";
			reg = <0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	gpio-keys {
		compatible = "gpio-keys";

		power {
			label = "Power";
			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
			linux,code = <KEY_POWER>;
			wakeup-source;
		};
	};

	panel: panel {
		compatible = "auo,b101aw03", "simple-panel";

		power-supply = <&vdd_pnl_reg>;
		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;

		backlight = <&backlight>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		vdd_5v0_reg: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "vdd_5v0";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-always-on;
		};

		regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "vdd_1v5";
			regulator-min-microvolt = <1500000>;
			regulator-max-microvolt = <1500000>;
			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
		};

		regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "vdd_1v2";
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		pci_vdd_reg: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "vdd_1v05";
			regulator-min-microvolt = <1050000>;
			regulator-max-microvolt = <1050000>;
			gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		vdd_pnl_reg: regulator@4 {
			compatible = "regulator-fixed";
			reg = <4>;
			regulator-name = "vdd_pnl";
			regulator-min-microvolt = <2800000>;
			regulator-max-microvolt = <2800000>;
			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		vdd_bl_reg: regulator@5 {
			compatible = "regulator-fixed";
			reg = <5>;
			regulator-name = "vdd_bl";
			regulator-min-microvolt = <2800000>;
			regulator-max-microvolt = <2800000>;
			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

		vdd_5v0_hdmi: regulator@6 {
			compatible = "regulator-fixed";
			reg = <6>;
			regulator-name = "VDDIO_HDMI";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
			enable-active-high;
			vin-supply = <&vdd_5v0_reg>;
		};
	};

	sound {
		compatible = "nvidia,tegra-audio-wm8903-harmony",
			     "nvidia,tegra-audio-wm8903";
		nvidia,model = "NVIDIA Tegra Harmony";

		nvidia,audio-routing =
			"Headphone Jack", "HPOUTR",
			"Headphone Jack", "HPOUTL",
			"Int Spk", "ROP",
			"Int Spk", "RON",
			"Int Spk", "LOP",
			"Int Spk", "LON",
			"Mic Jack", "MICBIAS",
			"IN1L", "Mic Jack";

		nvidia,i2s-controller = <&tegra_i2s1>;
		nvidia,audio-codec = <&wm8903>;

		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
			GPIO_ACTIVE_HIGH>;
		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
			GPIO_ACTIVE_HIGH>;
		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
			GPIO_ACTIVE_HIGH>;

		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
			 <&tegra_car TEGRA20_CLK_CDEV1>;
		clock-names = "pll_a", "pll_a_out0", "mclk";
	};
};
"hl com"> last packet */ if (lp->tx_end != last) { outw(lp->tx_last + XMT_CHAIN, ioaddr + HOST_ADDRESS_REG); outw(last, ioaddr + IO_PORT); } outw(lp->tx_last + XMT_COUNT, ioaddr + HOST_ADDRESS_REG); status = inw(ioaddr + IO_PORT); outw(status | CHAIN_BIT, ioaddr + IO_PORT); /* Continue the transmit command */ outb(RESUME_XMT_CMD, ioaddr); } lp->tx_last = last; lp->tx_end = end; if (net_debug > 5) printk(KERN_DEBUG "%s: exiting hardware_send_packet routine.\n", dev->name); return 0; } static void eepro_rx(struct net_device *dev) { struct eepro_local *lp = netdev_priv(dev); short ioaddr = dev->base_addr; short boguscount = 20; short rcv_car = lp->rx_start; unsigned rcv_event, rcv_status, rcv_next_frame, rcv_size; if (net_debug > 5) printk(KERN_DEBUG "%s: entering eepro_rx routine.\n", dev->name); /* Set the read pointer to the start of the RCV */ outw(rcv_car, ioaddr + HOST_ADDRESS_REG); rcv_event = inw(ioaddr + IO_PORT); while (rcv_event == RCV_DONE) { rcv_status = inw(ioaddr + IO_PORT); rcv_next_frame = inw(ioaddr + IO_PORT); rcv_size = inw(ioaddr + IO_PORT); if ((rcv_status & (RX_OK | RX_ERROR)) == RX_OK) { /* Malloc up new buffer. */ struct sk_buff *skb; dev->stats.rx_bytes+=rcv_size; rcv_size &= 0x3fff; skb = dev_alloc_skb(rcv_size+5); if (skb == NULL) { printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name); dev->stats.rx_dropped++; rcv_car = lp->rx_start + RCV_HEADER + rcv_size; lp->rx_start = rcv_next_frame; outw(rcv_next_frame, ioaddr + HOST_ADDRESS_REG); break; } skb_reserve(skb,2); if (lp->version == LAN595) insw(ioaddr+IO_PORT, skb_put(skb,rcv_size), (rcv_size + 3) >> 1); else { /* LAN595TX or LAN595FX, capable of 32-bit I/O processing */ unsigned short temp = inb(ioaddr + INT_MASK_REG); outb(temp | IO_32_BIT, ioaddr + INT_MASK_REG); insl(ioaddr+IO_PORT_32_BIT, skb_put(skb,rcv_size), (rcv_size + 3) >> 2); outb(temp & ~(IO_32_BIT), ioaddr + INT_MASK_REG); } skb->protocol = eth_type_trans(skb,dev); netif_rx(skb); dev->last_rx = jiffies; dev->stats.rx_packets++; } else { /* Not sure will ever reach here, I set the 595 to discard bad received frames */ dev->stats.rx_errors++; if (rcv_status & 0x0100) dev->stats.rx_over_errors++; else if (rcv_status & 0x0400) dev->stats.rx_frame_errors++; else if (rcv_status & 0x0800) dev->stats.rx_crc_errors++; printk(KERN_DEBUG "%s: event = %#x, status = %#x, next = %#x, size = %#x\n", dev->name, rcv_event, rcv_status, rcv_next_frame, rcv_size); } if (rcv_status & 0x1000) dev->stats.rx_length_errors++; rcv_car = lp->rx_start + RCV_HEADER + rcv_size; lp->rx_start = rcv_next_frame; if (--boguscount == 0) break; outw(rcv_next_frame, ioaddr + HOST_ADDRESS_REG); rcv_event = inw(ioaddr + IO_PORT); } if (rcv_car == 0) rcv_car = lp->rcv_upper_limit | 0xff; outw(rcv_car - 1, ioaddr + RCV_STOP); if (net_debug > 5) printk(KERN_DEBUG "%s: exiting eepro_rx routine.\n", dev->name); } static void eepro_transmit_interrupt(struct net_device *dev) { struct eepro_local *lp = netdev_priv(dev); short ioaddr = dev->base_addr; short boguscount = 25; short xmt_status; while ((lp->tx_start != lp->tx_end) && boguscount--) { outw(lp->tx_start, ioaddr + HOST_ADDRESS_REG); xmt_status = inw(ioaddr+IO_PORT); if (!(xmt_status & TX_DONE_BIT)) break; xmt_status = inw(ioaddr+IO_PORT); lp->tx_start = inw(ioaddr+IO_PORT); netif_wake_queue (dev); if (xmt_status & TX_OK) dev->stats.tx_packets++; else { dev->stats.tx_errors++; if (xmt_status & 0x0400) { dev->stats.tx_carrier_errors++; printk(KERN_DEBUG "%s: carrier error\n", dev->name); printk(KERN_DEBUG "%s: XMT status = %#x\n", dev->name, xmt_status); } else { printk(KERN_DEBUG "%s: XMT status = %#x\n", dev->name, xmt_status); printk(KERN_DEBUG "%s: XMT status = %#x\n", dev->name, xmt_status); } } if (xmt_status & 0x000f) { dev->stats.collisions += (xmt_status & 0x000f); } if ((xmt_status & 0x0040) == 0x0) { dev->stats.tx_heartbeat_errors++; } } } static int eepro_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) { struct eepro_local *lp = (struct eepro_local *)dev->priv; cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_Autoneg; cmd->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | ADVERTISED_Autoneg; if (GetBit(lp->word[5], ee_PortTPE)) { cmd->supported |= SUPPORTED_TP; cmd->advertising |= ADVERTISED_TP; } if (GetBit(lp->word[5], ee_PortBNC)) { cmd->supported |= SUPPORTED_BNC; cmd->advertising |= ADVERTISED_BNC; } if (GetBit(lp->word[5], ee_PortAUI)) { cmd->supported |= SUPPORTED_AUI; cmd->advertising |= ADVERTISED_AUI; } cmd->speed = SPEED_10; if (dev->if_port == TPE && lp->word[1] & ee_Duplex) { cmd->duplex = DUPLEX_FULL; } else { cmd->duplex = DUPLEX_HALF; } cmd->port = dev->if_port; cmd->phy_address = dev->base_addr; cmd->transceiver = XCVR_INTERNAL; if (lp->word[0] & ee_AutoNeg) { cmd->autoneg = 1; } return 0; } static void eepro_ethtool_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo) { strcpy(drvinfo->driver, DRV_NAME); strcpy(drvinfo->version, DRV_VERSION); sprintf(drvinfo->bus_info, "ISA 0x%lx", dev->base_addr); } static const struct ethtool_ops eepro_ethtool_ops = { .get_settings = eepro_ethtool_get_settings, .get_drvinfo = eepro_ethtool_get_drvinfo, }; #ifdef MODULE #define MAX_EEPRO 8 static struct net_device *dev_eepro[MAX_EEPRO]; static int io[MAX_EEPRO] = { [0 ... MAX_EEPRO-1] = -1 }; static int irq[MAX_EEPRO]; static int mem[MAX_EEPRO] = { /* Size of the rx buffer in KB */ [0 ... MAX_EEPRO-1] = RCV_DEFAULT_RAM/1024 }; static int autodetect; static int n_eepro; /* For linux 2.1.xx */ MODULE_AUTHOR("Pascal Dupuis and others"); MODULE_DESCRIPTION("Intel i82595 ISA EtherExpressPro10/10+ driver"); MODULE_LICENSE("GPL"); module_param_array(io, int, NULL, 0); module_param_array(irq, int, NULL, 0); module_param_array(mem, int, NULL, 0); module_param(autodetect, int, 0); MODULE_PARM_DESC(io, "EtherExpress Pro/10 I/O base addres(es)"); MODULE_PARM_DESC(irq, "EtherExpress Pro/10 IRQ number(s)"); MODULE_PARM_DESC(mem, "EtherExpress Pro/10 Rx buffer size(es) in kB (3-29)"); MODULE_PARM_DESC(autodetect, "EtherExpress Pro/10 force board(s) detection (0-1)"); int __init init_module(void) { struct net_device *dev; int i; if (io[0] == -1 && autodetect == 0) { printk(KERN_WARNING "eepro_init_module: Probe is very dangerous in ISA boards!\n"); printk(KERN_WARNING "eepro_init_module: Please add \"autodetect=1\" to force probe\n"); return -ENODEV; } else if (autodetect) { /* if autodetect is set then we must force detection */ for (i = 0; i < MAX_EEPRO; i++) { io[i] = 0; } printk(KERN_INFO "eepro_init_module: Auto-detecting boards (May God protect us...)\n"); } for (i = 0; io[i] != -1 && i < MAX_EEPRO; i++) { dev = alloc_etherdev(sizeof(struct eepro_local)); if (!dev) break; dev->mem_end = mem[i]; dev->base_addr = io[i]; dev->irq = irq[i]; if (do_eepro_probe(dev) == 0) { dev_eepro[n_eepro++] = dev; continue; } free_netdev(dev); break; } if (n_eepro) printk(KERN_INFO "%s", version); return n_eepro ? 0 : -ENODEV; } void __exit cleanup_module(void) { int i; for (i=0; i<n_eepro; i++) { struct net_device *dev = dev_eepro[i]; unregister_netdev(dev); release_region(dev->base_addr, EEPRO_IO_EXTENT); free_netdev(dev); } } #endif /* MODULE */