/*
* dts file for Hisilicon Hi6220 SoC
*
* Copyright (C) 2015, Hisilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi6220-clock.h>
#include <dt-bindings/pinctrl/hisi.h>
/ {
compatible = "hisilicon,hi6220";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <700>;
exit-latency-us = <250>;
min-residency-us = <1000>;
};
CLUSTER_SLEEP: cluster-sleep {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu4: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu5: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu6: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
cpu7: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
};
};
gic: interrupt-controller@f6801000 {
compatible = "arm,gic-400";
reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
<0x0 0xf6802000 0 0x2000>, /* GICC */
<0x0 0xf6804000 0 0x2000>, /* GICH */
<0x0 0xf6806000 0 0x2000>; /* GICV */
#address-cells = <0>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
#clock-cells = <1>;
};
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
media_ctrl: media_ctrl@f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0x0 0xf4410000 0x0 0x1000>;
#clock-cells = <1>;
};
pm_ctrl: pm_ctrl@f7032000 {
compatible = "hisilicon,hi6220-pmctrl", "syscon";
reg = <0x0 0xf7032000 0x0 0x1000>;
#clock-cells = <1>;
};
uart0: uart@f8015000 { /* console */
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf8015000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ao_ctrl HI6220_UART0_PCLK>,
<&ao_ctrl HI6220_UART0_PCLK>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@f7111000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7111000 0x0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART1_PCLK>,
<&sys_ctrl HI6220_UART1_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart2: uart@f7112000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7112000 0x0 0x1000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART2_PCLK>,
<&sys_ctrl HI6220_UART2_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
uart3: uart@f7113000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7113000 0x0 0x1000>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART3_PCLK>,
<&sys_ctrl HI6220_UART3_PCLK>;
clock-names = "uartclk", "apb_pclk";
};
uart4: uart@f7114000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0xf7114000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_ctrl HI6220_UART4_PCLK>,
<&sys_ctrl HI6220_UART4_PCLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
dual_timer0: timer@f8008000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x0 0xf8008000 0x0 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
<&ao_ctrl HI6220_TIMER0_PCLK>,
<&ao_ctrl HI6220_TIMER0_PCLK>;
clock-names = "timer1", "timer2", "apb_pclk";
};
pmx0: pinmux@f7010000 {
compatible = "pinctrl-single";
reg = <0x0 0xf7010000 0x0 0x27c>;
#address-cells = <1>;
#size-cells = <1>;
#gpio-range-cells = <3>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
pinctrl-single,gpio-range = <
&range 80 8 MUX_M0 /* gpio 3: [0..7] */
&range 88 8 MUX_M0 /* gpio 4: [0..7] */
&range 96 8 MUX_M0 /* gpio 5: [0..7] */
&range 104 8 MUX_M0 /* gpio 6: [0..7] */
&range 112 8 MUX_M0 /* gpio 7: [0..7] */
&range 120 2 MUX_M0 /* gpio 8: [0..1] */
&range 2 6 MUX_M1 /* gpio 8: [2..7] */
&range 8 8 MUX_M1 /* gpio 9: [0..7] */
&range 0 1 MUX_M1 /* gpio 10: [0] */
&range 16 7 MUX_M1 /* gpio 10: [1..7] */
&range 23 3 MUX_M1 /* gpio 11: [0..2] */
&range 28 5 MUX_M1 /* gpio 11: [3..7] */
&range 33 3 MUX_M1 /* gpio 12: [0..2] */
&range 43 5 MUX_M1 /* gpio 12: [3..7] */
&range 48 8 MUX_M1 /* gpio 13: [0..7] */
&range 56 8 MUX_M1 /* gpio 14: [0..7] */
&range 74 6 MUX_M1 /* gpio 15: [0..5] */
&range 122 1 MUX_M1 /* gpio 15: [6] */
&range 126 1 MUX_M1 /* gpio 15: [7] */
&range 127 8 MUX_M1 /* gpio 16: [0..7] */
&range 135 8 MUX_M1 /* gpio 17: [0..7] */
&range 143 8 MUX_M1 /* gpio 18: [0..7] */
&range 151 8 MUX_M1 /* gpio 19: [0..7] */
>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@f7010800 {
compatible = "pinconf-single";
reg = <0x0 0xf7010800 0x0 0x28c>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
};
pmx2: pinmux@f8001800 {
compatible = "pinconf-single";
reg = <0x0 0xf8001800 0x0 0x78>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-single,register-width = <32>;
};
gpio0: gpio@f8011000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8011000 0x0 0x1000>;
interrupts = <0 52 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio1: gpio@f8012000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8012000 0x0 0x1000>;
interrupts = <0 53 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio2: gpio@f8013000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8013000 0x0 0x1000>;
interrupts = <0 54 0x4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio3: gpio@f8014000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf8014000 0x0 0x1000>;
interrupts = <0 55 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 80 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio4: gpio@f7020000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7020000 0x0 0x1000>;
interrupts = <0 56 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 88 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio5: gpio@f7021000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7021000 0x0 0x1000>;
interrupts = <0 57 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 96 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio6: gpio@f7022000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7022000 0x0 0x1000>;
interrupts = <0 58 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 104 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio7: gpio@f7023000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7023000 0x0 0x1000>;
interrupts = <0 59 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 112 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio8: gpio@f7024000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7024000 0x0 0x1000>;
interrupts = <0 60 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio9: gpio@f7025000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7025000 0x0 0x1000>;
interrupts = <0 61 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 8 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio10: gpio@f7026000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7026000 0x0 0x1000>;
interrupts = <0 62 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio11: gpio@f7027000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7027000 0x0 0x1000>;
interrupts = <0 63 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio12: gpio@f7028000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7028000 0x0 0x1000>;
interrupts = <0 64 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio13: gpio@f7029000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf7029000 0x0 0x1000>;
interrupts = <0 65 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 48 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio14: gpio@f702a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702a000 0x0 0x1000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 56 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio15: gpio@f702b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702b000 0x0 0x1000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <
&pmx0 0 74 6
&pmx0 6 122 1
&pmx0 7 126 1
>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio16: gpio@f702c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702c000 0x0 0x1000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 127 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio17: gpio@f702d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702d000 0x0 0x1000>;
interrupts = <0 69 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 135 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio18: gpio@f702e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702e000 0x0 0x1000>;
interrupts = <0 70 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 143 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
gpio19: gpio@f702f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x0 0xf702f000 0x0 0x1000>;
interrupts = <0 71 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pmx0 0 151 8>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&ao_ctrl 2>;
clock-names = "apb_pclk";
};
spi0: spi@f7106000 {
compatible = "arm,pl022", "arm,primecell";
reg = <0x0 0xf7106000 0x0 0x1000>;
interrupts = <0 50 4>;
bus-id = <0>;
enable-dma = <0>;
clocks = <&sys_ctrl HI6220_SPI_CLK>;
clock-names = "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
num-cs = <1>;
cs-gpios = <&gpio6 2 0>;
status = "disabled";
};
};
};
