/*
* Autogenerated file by GPU Top : https://github.com/rib/gputop
* DO NOT EDIT manually!
*
*
* Copyright (c) 2015 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
*/
#include <linux/sysfs.h>
#include "i915_drv.h"
#include "i915_oa_chv.h"
enum metric_set_id {
METRIC_SET_ID_RENDER_BASIC = 1,
};
int i915_oa_n_builtin_metric_sets_chv = 1;
static const struct i915_oa_reg b_counter_config_render_basic[] = {
{ _MMIO(0x2740), 0x00000000 },
{ _MMIO(0x2710), 0x00000000 },
{ _MMIO(0x2714), 0x00800000 },
{ _MMIO(0x2720), 0x00000000 },
{ _MMIO(0x2724), 0x00800000 },
};
static const struct i915_oa_reg flex_eu_config_render_basic[] = {
{ _MMIO(0xe458), 0x00005004 },
{ _MMIO(0xe558), 0x00010003 },
{ _MMIO(0xe658), 0x00012011 },
{ _MMIO(0xe758), 0x00015014 },
{ _MMIO(0xe45c), 0x00051050 },
{ _MMIO(0xe55c), 0x00053052 },
{ _MMIO(0xe65c), 0x00055054 },
};
static const struct i915_oa_reg mux_config_render_basic[] = {
{ _MMIO(0x9888), 0x59800000 },
{ _MMIO(0x9888), 0x59800001 },
{ _MMIO(0x9888), 0x285a0006 },
{ _MMIO(0x9888), 0x2c110014 },
{ _MMIO(0x9888), 0x2e110000 },
{ _MMIO(0x9888), 0x2c310014 },
{ _MMIO(0x9888), 0x2e310000 },
{ _MMIO(0x9888), 0x2b8303df },
{ _MMIO(0x9888), 0x3580024f },
{ _MMIO(0x9888), 0x00580888 },
{ _MMIO(0x9888), 0x1e5a0015 },
{ _MMIO(0x9888), 0x205a0014 },
{ _MMIO(0x9888), 0x045a0000 },
{ _MMIO(0x9888), 0x025a0000 },
{ _MMIO(0x9888), 0x02180500 },
{ _MMIO(0x9888), 0x00190555 },
{ _MMIO(0x9888), 0x021d0500 },
{ _MMIO(0x9888), 0x021f0a00 },
{ _MMIO(0x9888), 0x00380444 },
{ _MMIO(0x9888), 0x02390500 },
{ _MMIO(0x9888), 0x003a0666 },
{ _MMIO(0x9888), 0x00100111 },
{ _MMIO(0x9888), 0x06110030 },
{ _MMIO(0x9888), 0x0a110031 },
{ _MMIO(0x9888), 0x0e110046 },
{ _MMIO(0x9888), 0x04110000 },
{ _MMIO(0x9888), 0x00110000 },
{ _MMIO(0x9888), 0x00130111 },
{ _MMIO(0x9888), 0x00300444 },
{ _MMIO(0x9888), 0x08310030 },
{ _MMIO(0x9888), 0x0c310031 },
{ _MMIO(0x9888), 0x10310046 },
{ _MMIO(0x9888), 0x04310000 },
{ _MMIO(0x9888), 0x00310000 },
{ _MMIO(0x9888), 0x00330444 },
{ _MMIO(0x9888), 0x038a0a00 },
{ _MMIO(0x9888), 0x018b0fff },
{ _MMIO(0x9888), 0x038b0a00 },
{ _MMIO(0x9888), 0x01855000 },
{ _MMIO(0x9888), 0x03850055 },
{ _MMIO(0x9888), 0x13830021 },
{ _MMIO(0x9888), 0x15830020 },
{ _MMIO(0x9888), 0x1783002f },
{ _MMIO(0x9888), 0x1983002e },
{ _MMIO(0x9888), 0x1b83002d },
{ _MMIO(0x9888), 0x1d83002c },
{ _MMIO(0x9888), 0x05830000 },
{ _MMIO(0x9888), 0x01840555 },
{ _MMIO(0x9888), 0x03840500 },
{ _MMIO(0x9888), 0x23800074 },
{ _MMIO(0x9888), 0x2580007d },
{ _MMIO(0x9888), 0x05800000 },
{ _MMIO(0x9888), 0x01805000 },
{ _MMIO(0x9888), 0x03800055 },
{ _MMIO(0x9888), 0x01865000 },
{ _MMIO(0x9888), 0x03860055 },
{ _MMIO(0x9888), 0x01875000 },
{ _MMIO(0x9888), 0x03870055 },
{ _MMIO(0x9888), 0x418000aa },
{ _MMIO(0x9888), 0x4380000a },
{ _MMIO(0x9888), 0x45800000 },
{ _MMIO(0x9888), 0x4780000a },
{ _MMIO(0x9888), 0x49800000 },
{ _MMIO(0x9888), 0x4b800000 },
{ _MMIO(0x9888), 0x4d800000 },
{ _MMIO(0x9888), 0x4f800000 },
{ _MMIO(0x9888), 0x51800000 },
{ _MMIO(0x9888), 0x53800000 },
{ _MMIO(0x9888), 0x55800000 },
{ _MMIO(0x9888), 0x57800000 },
{ _MMIO(0x9888), 0x59800000 },
};
static int
get_render_basic_mux_config(struct drm_i915_private *dev_priv,
const struct i915_oa_reg **regs,
int *lens)
{
int n = 0;
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
regs[n] = mux_config_render_basic;
lens[n] = ARRAY_SIZE(mux_config_render_basic);
n++;
return n;
}
int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv)
{
dev_priv->perf.oa.n_mux_configs = 0;
dev_priv->perf.oa.b_counter_regs = NULL;
dev_priv->perf.oa.b_counter_regs_len = 0;
dev_priv->perf.oa.flex_regs = NULL;
dev_priv->perf.oa.flex_regs_len = 0;
switch (dev_priv->perf.oa.metrics_set) {
case METRIC_SET_ID_RENDER_BASIC:
dev_priv->perf.oa.n_mux_configs =
get_render_basic_mux_config(dev_priv,
dev_priv->perf.oa.mux_regs,
dev_priv->perf.oa.mux_regs_lens);
if (dev_priv->perf.oa.n_mux_configs == 0) {
DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
/* EINVAL because *_register_sysfs already checked this
* and so it wouldn't have been advertised to userspace and
* so shouldn't have been requested
*/
return -EINVAL;
}
dev_priv->perf.oa.b_counter_regs =
b_counter_config_render_basic;
dev_priv->perf.oa.b_counter_regs_len =
ARRAY_SIZE(b_counter_config_render_basic);
dev_priv->perf.oa.flex_regs =
flex_eu_config_render_basic;
dev_priv->perf.oa.flex_regs_len =
ARRAY_SIZE(flex_eu_config_render_basic);
return 0;
default:
return -ENODEV;
}
}
static ssize_t
show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
{
return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
}
static struct device_attribute dev_attr_render_basic_id = {
.attr = { .name = "id", .mode = 0444 },
.show = show_render_basic_id,
.store = NULL,
};
static struct attribute *attrs_render_basic[] = {
&dev_attr_render_basic_id.attr,
NULL,
};
static struct attribute_group group_render_basic = {
.name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb",
.attrs = attrs_render_basic,
};
int
i915_perf_register_sysfs_chv(struct drm_i915_private *dev_priv)
{
const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
int ret = 0;
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
if (ret)
goto error_render_basic;
}
return 0;
error_render_basic:
return ret;
}
void
i915_perf_unregister_sysfs_chv(struct drm_i915_private *dev_priv)
{
const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
}
