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| author | Charles Hardin | 2012-09-05 21:19:48 +0200 |
|---|---|---|
| committer | John Crispin | 2012-11-09 11:37:16 +0100 |
| commit | 0f731711af2086e40a19420eddae1a589355e2ea (patch) | |
| tree | a1583a4d9a9be3347876eae1deb57f143c7ba51d | |
| parent | MIPS: tlbex: Fix section mismatches (diff) | |
| download | kernel-qcow2-linux-0f731711af2086e40a19420eddae1a589355e2ea.tar.gz kernel-qcow2-linux-0f731711af2086e40a19420eddae1a589355e2ea.tar.xz kernel-qcow2-linux-0f731711af2086e40a19420eddae1a589355e2ea.zip | |
mips/octeon: 16-Bit NOR flash was not being detected during boot
The cavium code assumed that all NOR on the boot bus was
an 8-bit NOR part and hardcoded the bankwidth. The simple
solution was to add the code that queries the configuration
register for the width of the bus that has been hardware strapped
to the Cavium. This allows both 8-bit and 16-bit parts to be
discovered during boot.
Acked-by: David Daney <david.daney@cavium.com>
Signed-off-by: Charles Hardin <ckhardin@exablox.com>
Patchwork: http://patchwork.linux-mips.org/patch/4323
Signed-off-by: John Crispin <blogic@openwrt.org>
| -rw-r--r-- | arch/mips/cavium-octeon/flash_setup.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c index e44a55bc7f0d..237e5b1a72d8 100644 --- a/arch/mips/cavium-octeon/flash_setup.c +++ b/arch/mips/cavium-octeon/flash_setup.c @@ -51,7 +51,8 @@ static int __init flash_init(void) flash_map.name = "phys_mapped_flash"; flash_map.phys = region_cfg.s.base << 16; flash_map.size = 0x1fc00000 - flash_map.phys; - flash_map.bankwidth = 1; + /* 8-bit bus (0 + 1) or 16-bit bus (1 + 1) */ + flash_map.bankwidth = region_cfg.s.width + 1; flash_map.virt = ioremap(flash_map.phys, flash_map.size); pr_notice("Bootbus flash: Setting flash for %luMB flash at " "0x%08llx\n", flash_map.size >> 20, flash_map.phys); |