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| author | Leonid Yegoshin | 2013-11-14 17:12:29 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2014-01-22 20:19:00 +0100 |
| commit | 198bb4cef13525dd9391623c514557123cc6cc31 (patch) | |
| tree | 8282a9e992fe0d756857f8e2846268ae9c945e2d | |
| parent | MIPS: kernel: cpu-probe: Add support for probing proAptiv cores (diff) | |
| download | kernel-qcow2-linux-198bb4cef13525dd9391623c514557123cc6cc31.tar.gz kernel-qcow2-linux-198bb4cef13525dd9391623c514557123cc6cc31.tar.xz kernel-qcow2-linux-198bb4cef13525dd9391623c514557123cc6cc31.zip | |
MIPS: Add function for flushing the TLB using the TLBINV instruction
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6136/
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0558f9b429ae..d9910a1e754a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -705,6 +705,19 @@ static inline int mm_insn_16bit(u16 insn) } /* + * TLB Invalidate Flush + */ +static inline void tlbinvf(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".word 0x42000004\n\t" /* tlbinvf */ + ".set pop"); +} + + +/* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit * performance counter number encoded into bits 1 ... 5 of the instruction. |