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| author | Peter De Schrijver | 2013-09-11 16:57:37 +0200 |
|---|---|---|
| committer | Peter De Schrijver | 2013-11-26 17:46:52 +0100 |
| commit | 2b239077d1e2061c65763dcf57ab978ae5261559 (patch) | |
| tree | e715f0da99334208a23cdfa9974ed5e3a2754bc8 | |
| parent | clk: tegra: Add support for PLLSS (diff) | |
| download | kernel-qcow2-linux-2b239077d1e2061c65763dcf57ab978ae5261559.tar.gz kernel-qcow2-linux-2b239077d1e2061c65763dcf57ab978ae5261559.tar.xz kernel-qcow2-linux-2b239077d1e2061c65763dcf57ab978ae5261559.zip | |
clk: tegra: Add periph regs bank X
Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
| -rw-r--r-- | drivers/clk/tegra/clk.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c index 14d25322aec5..a12a5f5107ec 100644 --- a/drivers/clk/tegra/clk.c +++ b/drivers/clk/tegra/clk.c @@ -57,6 +57,8 @@ #define RST_DEVICES_CLR_V 0x434 #define RST_DEVICES_SET_W 0x438 #define RST_DEVICES_CLR_W 0x43c +#define RST_DEVICES_SET_X 0x290 +#define RST_DEVICES_CLR_X 0x294 /* Global data of Tegra CPU CAR ops */ static struct tegra_cpu_car_ops dummy_car_ops; @@ -109,6 +111,14 @@ static struct tegra_clk_periph_regs periph_regs[] = { .rst_set_reg = RST_DEVICES_SET_W, .rst_clr_reg = RST_DEVICES_CLR_W, }, + [5] = { + .enb_reg = CLK_OUT_ENB_X, + .enb_set_reg = CLK_OUT_ENB_SET_X, + .enb_clr_reg = CLK_OUT_ENB_CLR_X, + .rst_reg = RST_DEVICES_X, + .rst_set_reg = RST_DEVICES_SET_X, + .rst_clr_reg = RST_DEVICES_CLR_X, + }, }; struct tegra_clk_periph_regs *get_reg_bank(int clkid) |