drm/amd/display: remove store clock state

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

11 files changed, 29 insertions, 161 deletions

diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
index fa88eb163ab8..446f50bb4e0a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
@@ -981,14 +981,10 @@ static bool construct(
 	/* get static clock information for PPLIB or firmware, save
 	 * max_clock_state
 	 */
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
-		enum clocks_state max_clocks_state =
+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+		pool->base.display_clock->max_clks_state =
 			dce110_resource_convert_clock_state_pp_to_dc(
 					static_clk_info.max_clocks_state);
-
-		pool->base.display_clock->funcs->store_max_clocks_state(
-				pool->base.display_clock, max_clocks_state);
-	}
 	{
 		struct irq_service_init_data init_data;
 		init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
index 6c713396e6ba..d5d888bdf882 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
@@ -1312,15 +1312,11 @@ static bool construct(
 	/* get static clock information for PPLIB or firmware, save
 	 * max_clock_state
 	 */
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
-		enum clocks_state max_clocks_state =
+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+		pool->base.display_clock->max_clks_state =
 			dce110_resource_convert_clock_state_pp_to_dc(
 					static_clk_info.max_clocks_state);
 
-		pool->base.display_clock->funcs->store_max_clocks_state(
-				pool->base.display_clock, max_clocks_state);
-	}
-
 	{
 		struct irq_service_init_data init_data;
 		init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
index 8792c4ed6e65..9903c9a4b8a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
@@ -1312,15 +1312,11 @@ static bool construct(
 	/* get static clock information for PPLIB or firmware, save
 	 * max_clock_state
 	 */
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
-		enum clocks_state max_clocks_state =
+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+		pool->base.display_clock->max_clks_state =
 			dce110_resource_convert_clock_state_pp_to_dc(
 					static_clk_info.max_clocks_state);
 
-		pool->base.display_clock->funcs->store_max_clocks_state(
-				pool->base.display_clock, max_clocks_state);
-	}
-
 	{
 		struct irq_service_init_data init_data;
 		init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
index 1e829f805d42..51721d10c811 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
@@ -975,15 +975,11 @@ static bool construct(
 	}
 
 
-	if (dm_pp_get_static_clocks(ctx, &static_clk_info)) {
-		enum clocks_state max_clocks_state =
+	if (dm_pp_get_static_clocks(ctx, &static_clk_info))
+		pool->base.display_clock->max_clks_state =
 				dce80_resource_convert_clock_state_pp_to_dc(
 					static_clk_info.max_clocks_state);
 
-		pool->base.display_clock->funcs->store_max_clocks_state(
-				pool->base.display_clock, max_clocks_state);
-	}
-
 	{
 		struct irq_service_init_data init_data;
 		init_data.ctx = dc->ctx;
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
index cc13afa326ad..ad7ebc1b434c 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.c
@@ -103,38 +103,6 @@ static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
  * static functions
  *****************************************************************************/
 
-/*
- * store_max_clocks_state
- *
- * @brief
- * Cache the clock state
- *
- * @param
- * struct display_clock *base - [out] cach the state in this structure
- * enum clocks_state max_clocks_state - [in] state to be stored
- */
-static void store_max_clocks_state(
-	struct display_clock *base,
-	enum clocks_state max_clocks_state)
-{
-	struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
-
-	switch (max_clocks_state) {
-	case CLOCKS_STATE_LOW:
-	case CLOCKS_STATE_NOMINAL:
-	case CLOCKS_STATE_PERFORMANCE:
-	case CLOCKS_STATE_ULTRA_LOW:
-		dc->max_clks_state = max_clocks_state;
-		break;
-
-	case CLOCKS_STATE_INVALID:
-	default:
-		/*Invalid Clocks State!*/
-		ASSERT_CRITICAL(false);
-		break;
-	}
-}
-
 static enum clocks_state get_min_clocks_state(struct display_clock *base)
 {
 	return base->cur_min_clks_state;
@@ -148,7 +116,7 @@ static bool set_min_clocks_state(
 	struct dm_pp_power_level_change_request level_change_req = {
 			DM_PP_POWER_LEVEL_INVALID};
 
-	if (clocks_state > dc->max_clks_state) {
+	if (clocks_state > base->max_clks_state) {
 		/*Requested state exceeds max supported state.*/
 		dm_logger_write(base->ctx->logger, LOG_WARNING,
 				"Requested state exceeds max supported state");
@@ -349,7 +317,7 @@ static enum clocks_state get_required_clocks_state(
 {
 	int32_t i;
 	struct display_clock_dce110 *disp_clk = DCLCK110_FROM_BASE(dc);
-	enum clocks_state low_req_clk = disp_clk->max_clks_state;
+	enum clocks_state low_req_clk = dc->max_clks_state;
 
 	if (!req_clocks) {
 		/* NULL pointer*/
@@ -363,7 +331,7 @@ static enum clocks_state get_required_clocks_state(
 	 * lowest RequiredState with the lowest state that satisfies
 	 * all required clocks
 	 */
-	for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+	for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
 		if ((req_clocks->display_clk_khz <=
 			max_clks_by_state[i].display_clk_khz) &&
 			(req_clocks->pixel_clk_khz <=
@@ -433,7 +401,7 @@ static void set_clock(
 				base->min_display_clk_threshold_khz);
 
 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
-	pxl_clk_params.pll_id = base->id;
+	pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 
 	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
 
@@ -459,8 +427,7 @@ static const struct display_clock_funcs funcs = {
 	.get_min_clocks_state = get_min_clocks_state,
 	.get_required_clocks_state = get_required_clocks_state,
 	.set_clock = set_clock,
-	.set_min_clocks_state = set_min_clocks_state,
-	.store_max_clocks_state = store_max_clocks_state
+	.set_min_clocks_state = set_min_clocks_state
 };
 
 static bool dal_display_clock_dce110_construct(
@@ -471,7 +438,6 @@ static bool dal_display_clock_dce110_construct(
 	struct dc_bios *bp = ctx->dc_bios;
 
 	dc_base->ctx = ctx;
-	dc_base->id = CLOCK_SOURCE_ID_DCPLL;
 	dc_base->min_display_clk_threshold_khz = 0;
 
 	dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
@@ -488,12 +454,11 @@ static bool dal_display_clock_dce110_construct(
 	dc110->gpu_pll_ss_divider = 1000;
 	dc110->ss_on_gpu_pll = false;
 
-	dc_base->id = CLOCK_SOURCE_ID_DFS;
 /* Initially set max clocks state to nominal.  This should be updated by
  * via a pplib call to DAL IRI eventually calling a
  * DisplayEngineClock_Dce110::StoreMaxClocksState().  This call will come in
  * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-	dc110->max_clks_state = CLOCKS_STATE_NOMINAL;
+	dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
 
 	dal_divider_range_construct(
 		&divider_ranges[DIVIDER_RANGE_01],
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
index 703cd656b5b0..50b51c41b0d9 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce110/display_clock_dce110.h
@@ -29,8 +29,6 @@
 
 struct display_clock_dce110 {
 	struct display_clock disp_clk_base;
-	/* Max display block clocks state*/
-	enum clocks_state max_clks_state;
 	bool use_max_disp_clk;
 	uint32_t dentist_vco_freq_khz;
 	/* Cache the status of DFS-bypass feature*/
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
index 665832b0718a..d8c8d8a1e2b3 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.c
@@ -72,41 +72,6 @@ enum divider_range_step_size {
 static struct divider_range divider_ranges[DIVIDER_RANGE_MAX];
 
 #define dce112_DFS_BYPASS_THRESHOLD_KHZ 400000
-/*****************************************************************************
- * static functions
- *****************************************************************************/
-
-/*
- * store_max_clocks_state
- *
- * @brief
- * Cache the clock state
- *
- * @param
- * struct display_clock *base - [out] cach the state in this structure
- * enum clocks_state max_clocks_state - [in] state to be stored
- */
-void dispclk_dce112_store_max_clocks_state(
-	struct display_clock *base,
-	enum clocks_state max_clocks_state)
-{
-	struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
-
-	switch (max_clocks_state) {
-	case CLOCKS_STATE_LOW:
-	case CLOCKS_STATE_NOMINAL:
-	case CLOCKS_STATE_PERFORMANCE:
-	case CLOCKS_STATE_ULTRA_LOW:
-		dc->max_clks_state = max_clocks_state;
-		break;
-
-	case CLOCKS_STATE_INVALID:
-	default:
-		/*Invalid Clocks State!*/
-		ASSERT_CRITICAL(false);
-		break;
-	}
-}
 
 enum clocks_state dispclk_dce112_get_min_clocks_state(
 	struct display_clock *base)
@@ -122,7 +87,7 @@ bool dispclk_dce112_set_min_clocks_state(
 	struct dm_pp_power_level_change_request level_change_req = {
 			DM_PP_POWER_LEVEL_INVALID};
 
-	if (clocks_state > dc->max_clks_state) {
+	if (clocks_state > base->max_clks_state) {
 		/*Requested state exceeds max supported state.*/
 		dm_logger_write(base->ctx->logger, LOG_WARNING,
 				"Requested state exceeds max supported state");
@@ -302,7 +267,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
 {
 	int32_t i;
 	struct display_clock_dce112 *disp_clk = DCLCK112_FROM_BASE(dc);
-	enum clocks_state low_req_clk = disp_clk->max_clks_state;
+	enum clocks_state low_req_clk = dc->max_clks_state;
 
 	if (!req_clocks) {
 		/* NULL pointer*/
@@ -316,7 +281,7 @@ enum clocks_state dispclk_dce112_get_required_clocks_state(
 	 * lowest RequiredState with the lowest state that satisfies
 	 * all required clocks
 	 */
-	for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+	for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
 		if ((req_clocks->display_clk_khz <=
 				(disp_clk->max_clks_by_state + i)->
 					display_clk_khz) &&
@@ -333,7 +298,6 @@ void dispclk_dce112_set_clock(
 	uint32_t requested_clk_khz)
 {
 	struct bp_set_dce_clock_parameters dce_clk_params;
-	struct display_clock_dce112 *dc = DCLCK112_FROM_BASE(base);
 	struct dc_bios *bp = base->ctx->dc_bios;
 
 	/* Prepare to program display clock*/
@@ -345,7 +309,7 @@ void dispclk_dce112_set_clock(
 				base->min_display_clk_threshold_khz);
 
 	dce_clk_params.target_clock_frequency = requested_clk_khz;
-	dce_clk_params.pll_id = dc->disp_clk_base.id;
+	dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 	dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
 
 	bp->funcs->set_dce_clock(bp, &dce_clk_params);
@@ -372,8 +336,7 @@ static const struct display_clock_funcs funcs = {
 	.get_min_clocks_state = dispclk_dce112_get_min_clocks_state,
 	.get_required_clocks_state = dispclk_dce112_get_required_clocks_state,
 	.set_clock = dispclk_dce112_set_clock,
-	.set_min_clocks_state = dispclk_dce112_set_min_clocks_state,
-	.store_max_clocks_state = dispclk_dce112_store_max_clocks_state,
+	.set_min_clocks_state = dispclk_dce112_set_min_clocks_state
 };
 
 bool dal_display_clock_dce112_construct(
@@ -399,12 +362,11 @@ bool dal_display_clock_dce112_construct(
 	dc112->gpu_pll_ss_divider = 1000;
 	dc112->ss_on_gpu_pll = false;
 
-	dc_base->id = CLOCK_SOURCE_ID_DFS;
 /* Initially set max clocks state to nominal.  This should be updated by
  * via a pplib call to DAL IRI eventually calling a
  * DisplayEngineClock_dce112::StoreMaxClocksState().  This call will come in
  * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-	dc112->max_clks_state = CLOCKS_STATE_NOMINAL;
+	dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
 
 	dc112->disp_clk_base.min_display_clk_threshold_khz =
 			(dc112->dentist_vco_freq_khz / 62);
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
index 34afff9a00bc..398af34720f7 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce112/display_clock_dce112.h
@@ -29,8 +29,6 @@
 
 struct display_clock_dce112 {
 	struct display_clock disp_clk_base;
-	/* Max display block clocks state*/
-	enum clocks_state max_clks_state;
 	bool use_max_disp_clk;
 	uint32_t dentist_vco_freq_khz;
 	/* Cache the status of DFS-bypass feature*/
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
index 89ee8bd96979..b101f7de2d11 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.c
@@ -95,28 +95,20 @@ static void set_clock(
 	uint32_t requested_clk_khz)
 {
 	struct bp_pixel_clock_parameters pxl_clk_params;
-	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
 	struct dc_bios *bp = dc->ctx->dc_bios;
 
 	/* Prepare to program display clock*/
 	memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
 
 	pxl_clk_params.target_pixel_clock = requested_clk_khz;
-	pxl_clk_params.pll_id = dc->id;
+	pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
 
 	bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
 
-	if (disp_clk->dfs_bypass_enabled) {
-
-		/* Cache the fixed display clock*/
-		disp_clk->dfs_bypass_disp_clk =
-			pxl_clk_params.dfs_bypass_display_clock;
-	}
-
 	/* from power down, we need mark the clock state as ClocksStateNominal
 	 * from HWReset, so when resume we will call pplib voltage regulator.*/
 	if (requested_clk_khz == 0)
-		disp_clk->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
+		dc->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
 }
 
 static enum clocks_state get_min_clocks_state(struct display_clock *dc)
@@ -131,8 +123,7 @@ static enum clocks_state get_required_clocks_state
 	struct state_dependent_clocks *req_clocks)
 {
 	int32_t i;
-	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-	enum clocks_state low_req_clk = disp_clk->max_clks_state;
+	enum clocks_state low_req_clk = dc->max_clks_state;
 
 	if (!req_clocks) {
 		/* NULL pointer*/
@@ -144,7 +135,7 @@ static enum clocks_state get_required_clocks_state
 	 * lowest RequiredState with the lowest state that satisfies
 	 * all required clocks
 	 */
-	for (i = disp_clk->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
+	for (i = dc->max_clks_state; i >= CLOCKS_STATE_ULTRA_LOW; --i) {
 		if ((req_clocks->display_clk_khz <=
 			max_clks_by_state[i].display_clk_khz) &&
 			(req_clocks->pixel_clk_khz <=
@@ -158,12 +149,10 @@ static bool set_min_clocks_state(
 	struct display_clock *dc,
 	enum clocks_state clocks_state)
 {
-	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
 	struct dm_pp_power_level_change_request level_change_req = {
 			DM_PP_POWER_LEVEL_INVALID};
 
-	if (clocks_state > disp_clk->max_clks_state) {
+	if (clocks_state > dc->max_clks_state) {
 		/*Requested state exceeds max supported state.*/
 		dm_logger_write(dc->ctx->logger, LOG_WARNING,
 				"Requested state exceeds max supported state");
@@ -271,28 +260,6 @@ static uint32_t get_dp_ref_clk_frequency(struct display_clock *dc)
 	return dp_ref_clk_khz;
 }
 
-static void store_max_clocks_state(
-	struct display_clock *dc,
-	enum clocks_state max_clocks_state)
-{
-	struct display_clock_dce80 *disp_clk = FROM_DISPLAY_CLOCK(dc);
-
-	switch (max_clocks_state) {
-	case CLOCKS_STATE_LOW:
-	case CLOCKS_STATE_NOMINAL:
-	case CLOCKS_STATE_PERFORMANCE:
-	case CLOCKS_STATE_ULTRA_LOW:
-		disp_clk->max_clks_state = max_clocks_state;
-		break;
-
-	case CLOCKS_STATE_INVALID:
-	default:
-		/*Invalid Clocks State!*/
-		BREAK_TO_DEBUGGER();
-		break;
-	}
-}
-
 static void display_clock_ss_construct(
 	struct display_clock_dce80 *disp_clk)
 {
@@ -411,8 +378,7 @@ static const struct display_clock_funcs funcs = {
 	.get_min_clocks_state = get_min_clocks_state,
 	.get_required_clocks_state = get_required_clocks_state,
 	.set_clock = set_clock,
-	.set_min_clocks_state = set_min_clocks_state,
-	.store_max_clocks_state = store_max_clocks_state
+	.set_min_clocks_state = set_min_clocks_state
 };
 
 
@@ -430,7 +396,6 @@ struct display_clock *dal_display_clock_dce80_create(
 	dc_base = &disp_clk->disp_clk;
 
 	dc_base->ctx = ctx;
-	dc_base->id = CLOCK_SOURCE_ID_DCPLL;
 	dc_base->min_display_clk_threshold_khz = 0;
 
 	dc_base->cur_min_clks_state = CLOCKS_STATE_INVALID;
@@ -450,12 +415,11 @@ struct display_clock *dal_display_clock_dce80_create(
 	disp_clk->dfs_bypass_disp_clk = 0;
 	disp_clk->use_max_disp_clk = true;/* false will hang the system! */
 
-	disp_clk->disp_clk.id = CLOCK_SOURCE_ID_DFS;
 /* Initially set max clocks state to nominal.  This should be updated by
  * via a pplib call to DAL IRI eventually calling a
  * DisplayEngineClock_Dce50::StoreMaxClocksState().  This call will come in
  * on PPLIB init. This is from DCE5x. in case HW wants to use mixed method.*/
-	disp_clk->max_clks_state = CLOCKS_STATE_NOMINAL;
+	dc_base->max_clks_state = CLOCKS_STATE_NOMINAL;
 /* Initially set current min clocks state to invalid since we
  * cannot make any assumption about PPLIB's initial state. This will be updated
  * by HWSS via SetMinClocksState() on first mode set prior to programming
diff --git a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
index 273a5d902840..1193398b5cea 100644
--- a/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
+++ b/drivers/gpu/drm/amd/display/dc/gpu/dce80/display_clock_dce80.h
@@ -37,8 +37,6 @@ struct display_clock_dce80 {
 	uint32_t gpu_pll_ss_divider;
 	/* Flag for Enabled SS on GPU PLL*/
 	bool ss_on_gpu_pll;
-	/* Max display block clocks state*/
-	enum clocks_state max_clks_state;
 	/* Current minimum display block clocks state*/
 	enum clocks_state cur_min_clks_state;
 	/* DFS-bypass feature variable
diff --git a/drivers/gpu/drm/amd/display/include/display_clock_interface.h b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
index a46ceebe2452..bc678a59a3c1 100644
--- a/drivers/gpu/drm/amd/display/include/display_clock_interface.h
+++ b/drivers/gpu/drm/amd/display/include/display_clock_interface.h
@@ -60,7 +60,8 @@ struct display_clock {
 	struct dc_context *ctx;
 	const struct display_clock_funcs *funcs;
 	uint32_t min_display_clk_threshold_khz;
-	enum clock_source_id id;
+	/* Max display block clocks state*/
+	enum clocks_state max_clks_state;
 
 	enum clocks_state cur_min_clks_state;
 };
@@ -77,8 +78,6 @@ struct display_clock_funcs {
 	bool (*set_min_clocks_state)(struct display_clock *disp_clk,
 		enum clocks_state clocks_state);
 	uint32_t (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk);
-	void (*store_max_clocks_state)(struct display_clock *disp_clk,
-		enum clocks_state max_clocks_state);
 
 };