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| author | Fabien Parent | 2019-05-02 14:18:42 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2019-06-07 00:56:09 +0200 |
| commit | 3d8b6e9c774ff57ad2860f79abd9cdb8f29ecaf8 (patch) | |
| tree | 49bdac1ad344f0402c29f5a6c21706a9d351db4c | |
| parent | Linux 5.2-rc1 (diff) | |
| download | kernel-qcow2-linux-3d8b6e9c774ff57ad2860f79abd9cdb8f29ecaf8.tar.gz kernel-qcow2-linux-3d8b6e9c774ff57ad2860f79abd9cdb8f29ecaf8.tar.xz kernel-qcow2-linux-3d8b6e9c774ff57ad2860f79abd9cdb8f29ecaf8.zip | |
dt-bindings: mediatek: audsys: add support for MT8516
Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/mt8516-clk.h | 17 |
2 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index f3cef1a6d95c..07c9d813465c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt8183-audiosys", "syscon" + - "mediatek,mt8516-audsys", "syscon" - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h index 9cfca53cd78d..816447b98edd 100644 --- a/include/dt-bindings/clock/mt8516-clk.h +++ b/include/dt-bindings/clock/mt8516-clk.h @@ -208,4 +208,21 @@ #define CLK_TOP_MSDC2_INFRA 176 #define CLK_TOP_NR_CLK 177 +/* AUDSYS */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_HDMI 7 +#define CLK_AUD_SPDF 8 +#define CLK_AUD_ADC 9 +#define CLK_AUD_DAC 10 +#define CLK_AUD_DAC_PREDIS 11 +#define CLK_AUD_TML 12 +#define CLK_AUD_NR_CLK 13 + #endif /* _DT_BINDINGS_CLK_MT8516_H */ |