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| author | Peter De Schrijver | 2017-07-25 12:34:09 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2017-08-24 00:59:42 +0200 |
| commit | 3dd065e70e6c6ec54d2fc7d5158d88518d3c5ab9 (patch) | |
| tree | 7238546e60d8885941db92b5b70f3196aa503587 | |
| parent | clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C (diff) | |
| download | kernel-qcow2-linux-3dd065e70e6c6ec54d2fc7d5158d88518d3c5ab9.tar.gz kernel-qcow2-linux-3dd065e70e6c6ec54d2fc7d5158d88518d3c5ab9.tar.xz kernel-qcow2-linux-3dd065e70e6c6ec54d2fc7d5158d88518d3c5ab9.zip | |
clk: tegra: change post IDDQ release delay to 5us
Increase delay after PLL IDDQ release to 5us per PLL specifications.
based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 1c36b8a72bd2..695ccb436cec 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw) val = pll_readl(pll->params->iddq_reg, pll); val &= ~BIT(pll->params->iddq_bit_idx); pll_writel(val, pll->params->iddq_reg, pll); - udelay(2); + udelay(5); } if (pll->params->reset_reg) { |