diff options
| author | Dmitry Osipenko | 2019-04-11 23:48:34 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2019-04-25 17:17:07 +0200 |
| commit | 40db569d6769ffa3864fd1b89616b1a7323568a8 (patch) | |
| tree | 9aa96c3dce3cb3ae8b56c71df77f0f6f5e3a10c3 | |
| parent | clk: tegra: Don't enable already enabled PLLs (diff) | |
| download | kernel-qcow2-linux-40db569d6769ffa3864fd1b89616b1a7323568a8.tar.gz kernel-qcow2-linux-40db569d6769ffa3864fd1b89616b1a7323568a8.tar.xz kernel-qcow2-linux-40db569d6769ffa3864fd1b89616b1a7323568a8.zip | |
clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider
There are wrongly set parenthesis in the code that are resulting in a
wrong configuration being programmed for PLLM. The original fix was made
by Danny Huang in the downstream kernel. The patch was tested on Nyan Big
Tegra124 chromebook, PLLM rate changing works correctly now and system
doesn't lock up after changing the PLLM rate due to EMC scaling.
Cc: <stable@vger.kernel.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index ebc8481a2122..6b976b2514f7 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -666,8 +666,8 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll, pll_override_writel(val, params->pmc_divp_reg, pll); val = pll_override_readl(params->pmc_divnm_reg, pll); - val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) | - ~(divn_mask(pll) << div_nmp->override_divn_shift); + val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | + (divn_mask(pll) << div_nmp->override_divn_shift)); val |= (cfg->m << div_nmp->override_divm_shift) | (cfg->n << div_nmp->override_divn_shift); pll_override_writel(val, params->pmc_divnm_reg, pll); |