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| author | Chris Wilson | 2017-10-04 14:41:52 +0200 |
|---|---|---|
| committer | Chris Wilson | 2017-10-04 16:05:40 +0200 |
| commit | 53221e11c7a0e85004c1a28f74e4e173f098d262 (patch) | |
| tree | 3891da9a6d4b94d961885d0a8063f69259b703ba | |
| parent | drm/i915: Transform whitelisting WAs into a simple reg write (diff) | |
| download | kernel-qcow2-linux-53221e11c7a0e85004c1a28f74e4e173f098d262.tar.gz kernel-qcow2-linux-53221e11c7a0e85004c1a28f74e4e173f098d262.tar.xz kernel-qcow2-linux-53221e11c7a0e85004c1a28f74e4e173f098d262.zip | |
drm/i915: Move MMCD_MISC_CTRL from context w/a to standard
Looking at gem_workarounds shows us that MMCD_MISC_CTRL is not restored
following a suspend-resume cycle. This implies that MMCD_MISC_CTRL is
not stored in the context, but is an ordinary register w/a that we need to
restore during init_hw.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171004124153.14142-1-chris@chris-wilson.co.uk
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_engine_cs.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a75f5e889927..8625feb0939e 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -980,7 +980,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine) GEN9_PBE_COMPRESSED_HASH_SELECTION); WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR); - WA_SET_BIT(MMCD_MISC_CTRL, MMCD_PCLA | MMCD_HOTSPOT_EN); + + I915_WRITE(MMCD_MISC_CTRL, + I915_READ(MMCD_MISC_CTRL) | + MMCD_PCLA | + MMCD_HOTSPOT_EN); } /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */ |