diff options
| author | Andre Przywara | 2009-07-03 16:00:14 +0200 |
|---|---|---|
| committer | Avi Kivity | 2009-09-10 07:33:08 +0200 |
| commit | 6098ca939ee5ceb81d6628b9130112516bae7400 (patch) | |
| tree | d68791f2575f444416061f1ae3a9ccfc8c4c9fd9 | |
| parent | KVM: Fix apic_mmio_write return for unaligned write (diff) | |
| download | kernel-qcow2-linux-6098ca939ee5ceb81d6628b9130112516bae7400.tar.gz kernel-qcow2-linux-6098ca939ee5ceb81d6628b9130112516bae7400.tar.xz kernel-qcow2-linux-6098ca939ee5ceb81d6628b9130112516bae7400.zip | |
KVM: handle AMD microcode MSR
Windows 7 tries to update the CPU's microcode on some processors,
so we ignore the MSR write here. The patchlevel register is already handled
(returning 0), because the MSR number is the same as Intel's.
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
| -rw-r--r-- | arch/x86/kvm/x86.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a50c83232e76..6dde99ca743e 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -861,6 +861,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data) case MSR_IA32_UCODE_REV: case MSR_IA32_UCODE_WRITE: case MSR_VM_HSAVE_PA: + case MSR_AMD64_PATCH_LOADER: break; case 0x200 ... 0x2ff: return set_msr_mtrr(vcpu, msr, data); |