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| author | Marek Szyprowski | 2017-01-26 13:37:53 +0100 |
|---|---|---|
| committer | Sylwester Nawrocki | 2017-01-27 11:34:00 +0100 |
| commit | 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317 (patch) | |
| tree | 4effec2a5d8cc0b65e1c9098537a7621491bfbf4 | |
| parent | clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks (diff) | |
| download | kernel-qcow2-linux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.tar.gz kernel-qcow2-linux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.tar.xz kernel-qcow2-linux-698e0d1d22346ef03d7a13fcd9c2cc86a24bf317.zip | |
clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
Default clock configuration applied by the bootloader for TM2 and TM2e
boards includes 250MHz and 278MHz rate for DISP PLL clock. To ensure
such configuration for those boards with 'assigned-clock-*' properties,
parameters for those two additional rates are needed.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5433.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index e11736f1625f..3feaea8be40e 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -739,7 +739,9 @@ static const struct samsung_pll_rate_table exynos5443_pll_rates[] __initconst = PLL_35XX_RATE(350000000U, 350, 6, 2), PLL_35XX_RATE(333000000U, 222, 4, 2), PLL_35XX_RATE(300000000U, 500, 5, 3), + PLL_35XX_RATE(278000000U, 556, 6, 3), PLL_35XX_RATE(266000000U, 532, 6, 3), + PLL_35XX_RATE(250000000U, 500, 6, 3), PLL_35XX_RATE(200000000U, 400, 6, 3), PLL_35XX_RATE(166000000U, 332, 6, 3), PLL_35XX_RATE(160000000U, 320, 6, 3), |