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| author | Leonid Yegoshin | 2013-11-14 17:12:25 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2014-01-22 20:18:59 +0100 |
| commit | 6e7f8b8e47ae581639c9c1c379bfb2e95c199842 (patch) | |
| tree | fb8d999155ba99504411c92ec0d6d63833d3682e | |
| parent | MIPS: features: Add initial support for Segmentation Control registers (diff) | |
| download | kernel-qcow2-linux-6e7f8b8e47ae581639c9c1c379bfb2e95c199842.tar.gz kernel-qcow2-linux-6e7f8b8e47ae581639c9c1c379bfb2e95c199842.tar.xz kernel-qcow2-linux-6e7f8b8e47ae581639c9c1c379bfb2e95c199842.zip | |
MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLB
For MIPS32R3 supported cores, the EHINV bit needs to be set when
invalidating the TLB. This is necessary because the legacy software
method of representing an invalid TLB entry using an unmapped address
value is not guaranteed to work.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6132/
| -rw-r--r-- | arch/mips/include/asm/tlb.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h index 235367cec4e6..4a2349302b55 100644 --- a/arch/mips/include/asm/tlb.h +++ b/arch/mips/include/asm/tlb.h @@ -18,7 +18,9 @@ */ #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) -#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) +#define UNIQUE_ENTRYHI(idx) \ + ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \ + (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) #include <asm-generic/tlb.h> |