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| author | Krzysztof Kozlowski | 2019-06-18 21:05:26 +0200 |
|---|---|---|
| committer | Sylwester Nawrocki | 2019-06-19 10:50:51 +0200 |
| commit | 7ef91224c4864202958b018cd5612db5cc9dc67d (patch) | |
| tree | 29ae0e063358fbc41ea8d035c8c4a5a668ee32c8 | |
| parent | clk: samsung: add new clocks for DMC for Exynos5422 SoC (diff) | |
| download | kernel-qcow2-linux-7ef91224c4864202958b018cd5612db5cc9dc67d.tar.gz kernel-qcow2-linux-7ef91224c4864202958b018cd5612db5cc9dc67d.tar.xz kernel-qcow2-linux-7ef91224c4864202958b018cd5612db5cc9dc67d.zip | |
clk: samsung: Add bus clock for GPU/G3D on Exynos4412
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| -rw-r--r-- | drivers/clk/samsung/clk-exynos4.c | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos4.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index d2a68a792a21..ed4af7da9c4f 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -961,6 +961,7 @@ static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { /* list of gate clocks supported in exynos4x12 soc */ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { + GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0), GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index a0439ce8e8d3..88ec3968b90a 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -187,6 +187,7 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 +#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ |