diff options
| author | Chris Wilson | 2010-10-22 15:59:29 +0200 |
|---|---|---|
| committer | Chris Wilson | 2010-10-22 16:04:09 +0200 |
| commit | 85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181 (patch) | |
| tree | e0fdb8cf1c837c9f9365e385346d353ca0cc80d5 | |
| parent | drm/i915: Fix flushing regression from 9af90d19f (diff) | |
| download | kernel-qcow2-linux-85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181.tar.gz kernel-qcow2-linux-85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181.tar.xz kernel-qcow2-linux-85ccc35b7e4a5e7894570fe9b4e4b56d82fc3181.zip | |
agp/intel: Restore valid PTE bit for Sandybridge after bdd3072
In cleaning up the mask functions in bdd3072, the setting of the PTE
valid bit was dropped for Sandybridge.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| -rw-r--r-- | drivers/char/agp/intel-gtt.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index 0c8ff6d8824b..6b6760ea2435 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -1211,13 +1211,13 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry, u32 pte_flags; if (type_mask == AGP_USER_UNCACHED_MEMORY) - pte_flags = GEN6_PTE_UNCACHED; + pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { - pte_flags = GEN6_PTE_LLC; + pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; if (gfdt) pte_flags |= GEN6_PTE_GFDT; } else { /* set 'normal'/'cached' to LLC by default */ - pte_flags = GEN6_PTE_LLC_MLC; + pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; if (gfdt) pte_flags |= GEN6_PTE_GFDT; } |