diff options
| author | Jianqun | 2014-10-20 11:55:03 +0200 |
|---|---|---|
| committer | Heiko Stuebner | 2014-10-20 13:53:56 +0200 |
| commit | 8f06f5d392b3fbd58a5d7e00b047b6ee08c6d9b0 (patch) | |
| tree | 5b864a527519ed47be96f419f43a378c2f4b226e | |
| parent | clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate (diff) | |
| download | kernel-qcow2-linux-8f06f5d392b3fbd58a5d7e00b047b6ee08c6d9b0.tar.gz kernel-qcow2-linux-8f06f5d392b3fbd58a5d7e00b047b6ee08c6d9b0.tar.xz kernel-qcow2-linux-8f06f5d392b3fbd58a5d7e00b047b6ee08c6d9b0.zip | |
clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout
Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.
Tested on rk3288 board, suggested by Heiko.
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3288.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index c3706431ed10..d417bceac9e4 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -307,7 +307,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { RK3288_CLKGATE_CON(4), 2, GFLAGS), MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT, RK3288_CLKSEL_CON(4), 8, 2, MFLAGS), - COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, CLK_SET_RATE_PARENT, + COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0, RK3288_CLKSEL_CON(4), 12, 1, MFLAGS, RK3288_CLKGATE_CON(4), 0, GFLAGS), GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT, |