diff options
| author | Alex Deucher | 2017-08-24 22:46:29 +0200 |
|---|---|---|
| committer | Alex Deucher | 2017-08-29 21:27:58 +0200 |
| commit | 925d5d798f465671c6b8011e80c636da46ef1a16 (patch) | |
| tree | 912931a9baa18e74e55ce7fd64235afd7f3071e7 | |
| parent | drm/amdgpu/powerplay/vega10: fix typo in register base index (diff) | |
| download | kernel-qcow2-linux-925d5d798f465671c6b8011e80c636da46ef1a16.tar.gz kernel-qcow2-linux-925d5d798f465671c6b8011e80c636da46ef1a16.tar.xz kernel-qcow2-linux-925d5d798f465671c6b8011e80c636da46ef1a16.zip | |
drm/amdgpu/gfx8: apply dynamic cu mask to APUs as well
Confirmed with the hw team. It's the same for all asics.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 775484639f79..6666fcd8b08f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4622,12 +4622,10 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) mqd->compute_static_thread_mgmt_se2 = 0xffffffff; mqd->compute_static_thread_mgmt_se3 = 0xffffffff; mqd->compute_misc_reserved = 0x00000003; - if (!(adev->flags & AMD_IS_APU)) { - mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr - + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); - mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr - + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); - } + mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr + + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); + mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr + + offsetof(struct vi_mqd_allocation, dynamic_cu_mask)); eop_base_addr = ring->eop_gpu_addr >> 8; mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); |