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| author | Tony Lindgren | 2015-05-20 18:01:20 +0200 |
|---|---|---|
| committer | Tony Lindgren | 2015-05-20 18:01:20 +0200 |
| commit | 928f81aa619d845d6faa5a459cdbc18b7a78ddce (patch) | |
| tree | 14f5456843c82c786cc79fb248b002a22b2766e6 | |
| parent | Linux 4.1-rc3 (diff) | |
| download | kernel-qcow2-linux-928f81aa619d845d6faa5a459cdbc18b7a78ddce.tar.gz kernel-qcow2-linux-928f81aa619d845d6faa5a459cdbc18b7a78ddce.tar.xz kernel-qcow2-linux-928f81aa619d845d6faa5a459cdbc18b7a78ddce.zip | |
ARM: OMAP1: Move UART defines to prepare for sparse IRQ
These have been indirectly included via asm/irqs.h that
has included mach/hardware.h unless SPARSE_IRQ is specified.
Let's move them to where the other OMAP serial defines for
8250 are.
Cc: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
| -rw-r--r-- | arch/arm/mach-omap1/include/mach/serial.h | 5 | ||||
| -rw-r--r-- | include/uapi/linux/serial_reg.h | 3 |
2 files changed, 3 insertions, 5 deletions
diff --git a/arch/arm/mach-omap1/include/mach/serial.h b/arch/arm/mach-omap1/include/mach/serial.h index 2ce6a2db470b..4700e384c3d9 100644 --- a/arch/arm/mach-omap1/include/mach/serial.h +++ b/arch/arm/mach-omap1/include/mach/serial.h @@ -27,11 +27,6 @@ */ #define OMAP_UART_INFO_OFS 0x3ffc -/* OMAP1 serial ports */ -#define OMAP1_UART1_BASE 0xfffb0000 -#define OMAP1_UART2_BASE 0xfffb0800 -#define OMAP1_UART3_BASE 0xfffb9800 - #define OMAP_PORT_SHIFT 2 #define OMAP7XX_PORT_SHIFT 0 diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h index e9b4cb0cd7ed..1e5ac4e776da 100644 --- a/include/uapi/linux/serial_reg.h +++ b/include/uapi/linux/serial_reg.h @@ -331,6 +331,9 @@ * Extra serial register definitions for the internal UARTs * in TI OMAP processors. */ +#define OMAP1_UART1_BASE 0xfffb0000 +#define OMAP1_UART2_BASE 0xfffb0800 +#define OMAP1_UART3_BASE 0xfffb9800 #define UART_OMAP_MDR1 0x08 /* Mode definition register */ #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ #define UART_OMAP_SCR 0x10 /* Supplementary control register */ |