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| author | Tirumalesh Chalamarla | 2015-09-22 19:59:48 +0200 |
|---|---|---|
| committer | Catalin Marinas | 2015-10-28 20:09:17 +0100 |
| commit | 97303480753e48fb313dc0e15daaf11b0451cdb8 (patch) | |
| tree | 6fd24b7c6fa67a31225a1528b0e2b8ee11b1bbd0 | |
| parent | arm64: remove bogus TASK_SIZE_64 check (diff) | |
| download | kernel-qcow2-linux-97303480753e48fb313dc0e15daaf11b0451cdb8.tar.gz kernel-qcow2-linux-97303480753e48fb313dc0e15daaf11b0451cdb8.tar.xz kernel-qcow2-linux-97303480753e48fb313dc0e15daaf11b0451cdb8.zip | |
arm64: Increase the max granular size
Increase the standard cacheline size to avoid having locks in the same
cacheline.
Cavium's ThunderX core implements cache lines of 128 byte size. With
current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could
share the same cache line leading a performance degradation.
Increasing the size fixes that.
Increasing the size has no negative impact to cache invalidation on
systems with a smaller cache line. There is an impact on memory usage,
but that's not too important for arm64 use cases.
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@cavium.com>
Signed-off-by: Robert Richter <rrichter@cavium.com>
Acked-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm64/include/asm/cache.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index bde449936e2f..5082b30bc2c0 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -18,7 +18,7 @@ #include <asm/cachetype.h> -#define L1_CACHE_SHIFT 6 +#define L1_CACHE_SHIFT 7 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) /* |