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author | Markos Chandras | 2014-12-03 13:31:42 +0100 |
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committer | Markos Chandras | 2015-02-17 16:37:36 +0100 |
commit | b55b9e271544a23ca23b7ca3a87baf6329fcb341 (patch) | |
tree | 08fe2d9e08d12039c92ff2d722f057f36c048dd9 | |
parent | MIPS: Add LLB bit and related feature for the Config 5 CP0 register (diff) | |
download | kernel-qcow2-linux-b55b9e271544a23ca23b7ca3a87baf6329fcb341.tar.gz kernel-qcow2-linux-b55b9e271544a23ca23b7ca3a87baf6329fcb341.tar.xz kernel-qcow2-linux-b55b9e271544a23ca23b7ca3a87baf6329fcb341.zip |
MIPS: asm: mipsregs: Add support for the LLADDR register
If Config5/LLB is set in the core, then software can write the LLB
bit in the LLADDR register.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
-rw-r--r-- | arch/mips/include/asm/mipsregs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 093cd70e56ec..06346001ee4d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1128,6 +1128,8 @@ do { \ #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) +#define read_c0_lladdr() __read_ulong_c0_register($17, 0) +#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val) #define read_c0_maar() __read_ulong_c0_register($17, 1) #define write_c0_maar(val) __write_ulong_c0_register($17, 1, val) #define read_c0_maari() __read_32bit_c0_register($17, 2) |