diff options
| author | Andi Kleen | 2006-03-25 16:31:31 +0100 |
|---|---|---|
| committer | Linus Torvalds | 2006-03-25 18:14:38 +0100 |
| commit | ba22f13563de5773701fc318ccaaa37b1fb6d294 (patch) | |
| tree | e29ddeaca4c9f7b1b5ef08804980600d0e089f5b | |
| parent | [PATCH] i386/x86-64: List Intel LaGrange AKA SMX in /proc/cpuinfo (diff) | |
| download | kernel-qcow2-linux-ba22f13563de5773701fc318ccaaa37b1fb6d294.tar.gz kernel-qcow2-linux-ba22f13563de5773701fc318ccaaa37b1fb6d294.tar.xz kernel-qcow2-linux-ba22f13563de5773701fc318ccaaa37b1fb6d294.zip | |
[PATCH] x86_64: Remove CONFIG_UNORDERED_IO
It was a failed experiment - all benchmarks done with it on both AMD
and Intel showed it was a loss. That was probably because the store
buffers of the CPUs for write combining traffic weren't large enough.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
| -rw-r--r-- | arch/x86_64/Kconfig | 10 | ||||
| -rw-r--r-- | include/asm-x86_64/io.h | 18 |
2 files changed, 0 insertions, 28 deletions
diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig index 6fc631457196..31bab721cb71 100644 --- a/arch/x86_64/Kconfig +++ b/arch/x86_64/Kconfig @@ -520,16 +520,6 @@ config PCI_MMCONFIG bool "Support mmconfig PCI config space access" depends on PCI && ACPI -config UNORDERED_IO - bool "Unordered IO mapping access" - depends on EXPERIMENTAL - help - Use unordered stores to access IO memory mappings in device drivers. - Still very experimental. When a driver works on IA64/ppc64/pa-risc it should - work with this option, but it makes the drivers behave differently - from i386. Requires that the driver writer used memory barriers - properly. - source "drivers/pci/pcie/Kconfig" source "drivers/pci/Kconfig" diff --git a/include/asm-x86_64/io.h b/include/asm-x86_64/io.h index ac12bda3bb1f..cafdfb37f0d8 100644 --- a/include/asm-x86_64/io.h +++ b/include/asm-x86_64/io.h @@ -200,23 +200,6 @@ static inline __u64 __readq(const volatile void __iomem *addr) #define mmiowb() -#ifdef CONFIG_UNORDERED_IO -static inline void __writel(__u32 val, volatile void __iomem *addr) -{ - volatile __u32 __iomem *target = addr; - asm volatile("movnti %1,%0" - : "=m" (*target) - : "r" (val) : "memory"); -} - -static inline void __writeq(__u64 val, volatile void __iomem *addr) -{ - volatile __u64 __iomem *target = addr; - asm volatile("movnti %1,%0" - : "=m" (*target) - : "r" (val) : "memory"); -} -#else static inline void __writel(__u32 b, volatile void __iomem *addr) { *(__force volatile __u32 *)addr = b; @@ -225,7 +208,6 @@ static inline void __writeq(__u64 b, volatile void __iomem *addr) { *(__force volatile __u64 *)addr = b; } -#endif static inline void __writeb(__u8 b, volatile void __iomem *addr) { *(__force volatile __u8 *)addr = b; |