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| author | John Crispin | 2013-03-21 19:01:49 +0100 |
|---|---|---|
| committer | Ralf Baechle | 2013-05-08 01:19:07 +0200 |
| commit | bb19fea238daead66ab3630ad09fba50aa563048 (patch) | |
| tree | c35ef0b816ffe5568d964b9ba3792bb84bcf317c | |
| parent | MIPS: ralink: add PCI IRQ handling (diff) | |
| download | kernel-qcow2-linux-bb19fea238daead66ab3630ad09fba50aa563048.tar.gz kernel-qcow2-linux-bb19fea238daead66ab3630ad09fba50aa563048.tar.xz kernel-qcow2-linux-bb19fea238daead66ab3630ad09fba50aa563048.zip | |
MIPS: ralink: add RT3352 register defines
Add a few missing defines that are needed to make USB and clock detection work
on the RT3352.
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5166/
| -rw-r--r-- | arch/mips/include/asm/mach-ralink/rt305x.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index 7d344f2d7d0a..e36c3c529423 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void) #define RT305X_GPIO_MODE_SDRAM BIT(8) #define RT305X_GPIO_MODE_RGMII BIT(9) +#define RT3352_SYSC_REG_SYSCFG0 0x010 +#define RT3352_SYSC_REG_SYSCFG1 0x014 +#define RT3352_SYSC_REG_CLKCFG1 0x030 +#define RT3352_SYSC_REG_RSTCTRL 0x034 +#define RT3352_SYSC_REG_USB_PS 0x05c + +#define RT3352_CLKCFG0_XTAL_SEL BIT(20) +#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18) +#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20) +#define RT3352_RSTCTRL_UHST BIT(22) +#define RT3352_RSTCTRL_UDEV BIT(25) +#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10) + #endif |