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| author | Peter De Schrijver | 2017-07-25 12:34:06 +0200 |
|---|---|---|
| committer | Stephen Boyd | 2017-08-24 00:59:15 +0200 |
| commit | bc7b34a2fb78661b2980d949aad8edc39c253e3a (patch) | |
| tree | a518f04fca7e3146d3ba85d0f49550cb737155b1 | |
| parent | clk: tegra210: remove non-existing VFIR clock (diff) | |
| download | kernel-qcow2-linux-bc7b34a2fb78661b2980d949aad8edc39c253e3a.tar.gz kernel-qcow2-linux-bc7b34a2fb78661b2980d949aad8edc39c253e3a.tar.xz kernel-qcow2-linux-bc7b34a2fb78661b2980d949aad8edc39c253e3a.zip | |
clk: tegra: Init cfg structure in _get_pll_mnp
Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.
Based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index fbd8726213ab..1c36b8a72bd2 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -690,6 +690,8 @@ static void _get_pll_mnp(struct tegra_clk_pll *pll, struct tegra_clk_pll_params *params = pll->params; struct div_nmp *div_nmp = params->div_nmp; + *cfg = (struct tegra_clk_pll_freq_table) { }; + if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && (pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) { |