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authorAnusha Srivatsa2017-06-10 00:26:10 +0200
committerRodrigo Vivi2017-06-12 18:44:34 +0200
commitcebfcead63de6f6b1414c3b58ee554b5fc8e103c (patch)
tree7f5641cbcbba83b08b87316f89b7645648129736
parentdrm/i915/cnl: Enable loadgen_select bit for vswing sequence (diff)
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drm/i915/DMC/CNL: Load DMC on CNL
This patch loads the DMC on CNL.The firmware version is 1.04. v2: (Rodrigo) Remove MODULE_FIRMWARE. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-13-git-send-email-rodrigo.vivi@intel.com
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c1
-rw-r--r--drivers/gpu/drm/i915/intel_csr.c11
2 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 03b5fe3e3036..506ec32b9e53 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -445,6 +445,7 @@ static const struct intel_device_info intel_cannonlake_info = {
.platform = INTEL_CANNONLAKE,
.gen = 10,
.ddb_size = 1024,
+ .has_csr = 1,
};
/*
diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c
index fb6af0bcdf8f..dedc5dff9fd3 100644
--- a/drivers/gpu/drm/i915/intel_csr.c
+++ b/drivers/gpu/drm/i915/intel_csr.c
@@ -37,6 +37,9 @@
#define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin"
#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
+#define I915_CSR_CNL "i915/cnl_dmc_ver1_04.bin"
+#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
+
#define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin"
MODULE_FIRMWARE(I915_CSR_KBL);
#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
@@ -289,7 +292,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
csr->version = css_header->version;
- if (IS_GEMINILAKE(dev_priv)) {
+ if (IS_CANNONLAKE(dev_priv)) {
+ required_version = CNL_CSR_VERSION_REQUIRED;
+ } else if (IS_GEMINILAKE(dev_priv)) {
required_version = GLK_CSR_VERSION_REQUIRED;
} else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
required_version = KBL_CSR_VERSION_REQUIRED;
@@ -438,7 +443,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
if (!HAS_CSR(dev_priv))
return;
- if (IS_GEMINILAKE(dev_priv))
+ if (IS_CANNONLAKE(dev_priv))
+ csr->fw_path = I915_CSR_CNL;
+ else if (IS_GEMINILAKE(dev_priv))
csr->fw_path = I915_CSR_GLK;
else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
csr->fw_path = I915_CSR_KBL;