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| author | Will Deacon | 2015-09-02 19:49:28 +0200 |
|---|---|---|
| committer | Will Deacon | 2015-09-15 16:50:01 +0200 |
| commit | d10bcd473301888f957ec4b6b12aa3621be78d59 (patch) | |
| tree | a9297efb6b822cbfd6dca8101d3dfd4dba92faea | |
| parent | arm64: enable generic idle loop (diff) | |
| download | kernel-qcow2-linux-d10bcd473301888f957ec4b6b12aa3621be78d59.tar.gz kernel-qcow2-linux-d10bcd473301888f957ec4b6b12aa3621be78d59.tar.xz kernel-qcow2-linux-d10bcd473301888f957ec4b6b12aa3621be78d59.zip | |
arm64: head.S: initialise mdcr_el2 in el2_setup
When entering the kernel at EL2, we fail to initialise the MDCR_EL2
register which controls debug access and PMU capabilities at EL1.
This patch ensures that the register is initialised so that all traps
are disabled and all the PMU counters are available to the host. When a
guest is scheduled, KVM takes care to configure trapping appropriately.
Cc: <stable@vger.kernel.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | arch/arm64/kernel/head.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index a055be6125cf..90d09eddd5b2 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -523,6 +523,11 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and E0E on LE systems msr hstr_el2, xzr // Disable CP15 traps to EL2 #endif + /* EL2 debug */ + mrs x0, pmcr_el0 // Disable debug access traps + ubfx x0, x0, #11, #5 // to EL2 and allow access to + msr mdcr_el2, x0 // all PMU counters from EL1 + /* Stage-2 translation */ msr vttbr_el2, xzr |