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| author | Damien Lespiau | 2015-02-09 20:33:21 +0100 |
|---|---|---|
| committer | Daniel Vetter | 2015-02-13 23:28:36 +0100 |
| commit | e2db7071f14b7ac095a24448e9edd036ba332da3 (patch) | |
| tree | 1a20aeeea7f1a98a5dda8a38ff0321b0dfc1db19 | |
| parent | drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS (diff) | |
| download | kernel-qcow2-linux-e2db7071f14b7ac095a24448e9edd036ba332da3.tar.gz kernel-qcow2-linux-e2db7071f14b7ac095a24448e9edd036ba332da3.tar.xz kernel-qcow2-linux-e2db7071f14b7ac095a24448e9edd036ba332da3.zip | |
drm/i915/skl: Implement WaCcsTlbPrefetchDisable:skl
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ecc14f558744..8c9e15073e38 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6209,6 +6209,7 @@ enum skl_disp_power_wells { #define GEN9_HALF_SLICE_CHICKEN5 0xe188 #define GEN9_DG_MIRROR_FIX_ENABLE (1<<5) +#define GEN9_CCS_TLB_PREFETCH_ENABLE (1<<3) #define GEN8_ROW_CHICKEN 0xe4f0 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 29873ff2dd8d..3c66d80d050a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -984,6 +984,10 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) /* WaDisablePartialResolveInVc:skl */ WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE); + /* WaCcsTlbPrefetchDisable:skl */ + WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, + GEN9_CCS_TLB_PREFETCH_ENABLE); + return 0; } |