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| author | Suzuki K Poulose | 2018-03-12 11:04:14 +0100 |
|---|---|---|
| committer | Will Deacon | 2018-03-19 19:14:27 +0100 |
| commit | 7206dc93a58fb76421c4411eefa3c003337bcb2d (patch) | |
| tree | 9bf4f279e538a41472bf6f5e8e3088645c86f8b0 /Documentation/arm64/cpu-feature-registers.txt | |
| parent | arm64: Documentation: cpu-feature-registers: Remove RES0 fields (diff) | |
| download | kernel-qcow2-linux-7206dc93a58fb76421c4411eefa3c003337bcb2d.tar.gz kernel-qcow2-linux-7206dc93a58fb76421c4411eefa3c003337bcb2d.tar.xz kernel-qcow2-linux-7206dc93a58fb76421c4411eefa3c003337bcb2d.zip | |
arm64: Expose Arm v8.4 features
Expose the new features introduced by Arm v8.4 extensions to
Arm v8-A profile.
These include :
1) Data indpendent timing of instructions. (DIT, exposed as HWCAP_DIT)
2) Unaligned atomic instructions and Single-copy atomicity of loads
and stores. (AT, expose as HWCAP_USCAT)
3) LDAPR and STLR instructions with immediate offsets (extension to
LRCPC, exposed as HWCAP_ILRCPC)
4) Flag manipulation instructions (TS, exposed as HWCAP_FLAGM).
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/arm64/cpu-feature-registers.txt')
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt index 22cfb86143ee..7964f03846b1 100644 --- a/Documentation/arm64/cpu-feature-registers.txt +++ b/Documentation/arm64/cpu-feature-registers.txt @@ -110,6 +110,7 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| + | TS | [55-52] | y | |--------------------------------------------------| | FHM | [51-48] | y | |--------------------------------------------------| @@ -139,6 +140,7 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| + | DIT | [51-48] | y | |--------------------------------------------------| | SVE | [35-32] | y | |--------------------------------------------------| @@ -191,6 +193,14 @@ infrastructure: | DPB | [3-0] | y | x--------------------------------------------------x + 5) ID_AA64MMFR2_EL1 - Memory model feature register 2 + + x--------------------------------------------------x + | Name | bits | visible | + |--------------------------------------------------| + | AT | [35-32] | y | + x--------------------------------------------------x + Appendix I: Example --------------------------- |