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| author | Suzuki K Poulose | 2017-03-14 19:13:25 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2017-03-20 17:29:28 +0100 |
| commit | c8c3798d2369e4285da44b244638eafe446a8f8a (patch) | |
| tree | 484cfb45948628e4945cd808d26efeb1021105e7 /Documentation/arm64/cpu-feature-registers.txt | |
| parent | arm64: KVM: Add support for VPIPT I-caches (diff) | |
| download | kernel-qcow2-linux-c8c3798d2369e4285da44b244638eafe446a8f8a.tar.gz kernel-qcow2-linux-c8c3798d2369e4285da44b244638eafe446a8f8a.tar.xz kernel-qcow2-linux-c8c3798d2369e4285da44b244638eafe446a8f8a.zip | |
arm64: v8.3: Support for Javascript conversion instruction
ARMv8.3 adds support for a new instruction to perform conversion
from double precision floating point to integer to match the
architected behaviour of the equivalent Javascript conversion.
Expose the availability via HWCAP and MRS emulation.
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64/cpu-feature-registers.txt')
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt index 61ca21ebef1a..5b279dcee9c6 100644 --- a/Documentation/arm64/cpu-feature-registers.txt +++ b/Documentation/arm64/cpu-feature-registers.txt @@ -169,6 +169,14 @@ infrastructure: as available on the CPU where it is fetched and is not a system wide safe value. + 4) ID_AA64ISAR1_EL1 - Instruction set attribute register 1 + + x--------------------------------------------------x + | Name | bits | visible | + |--------------------------------------------------| + | JSCVT | [15-12] | y | + x--------------------------------------------------x + Appendix I: Example --------------------------- |