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| author | Steve Capper | 2018-01-24 09:27:08 +0100 |
|---|---|---|
| committer | Catalin Marinas | 2018-01-26 19:23:17 +0100 |
| commit | ec89ab50a03a33a4a648869e868b1964354fb2d1 (patch) | |
| tree | fca3a39f0042db178584d91eef67f046abe3c2ab /Documentation/arm64 | |
| parent | arm64: Turn on KPTI only on CPUs that need it (diff) | |
| download | kernel-qcow2-linux-ec89ab50a03a33a4a648869e868b1964354fb2d1.tar.gz kernel-qcow2-linux-ec89ab50a03a33a4a648869e868b1964354fb2d1.tar.xz kernel-qcow2-linux-ec89ab50a03a33a4a648869e868b1964354fb2d1.zip | |
arm64: Fix TTBR + PAN + 52-bit PA logic in cpu_do_switch_mm
In cpu_do_switch_mm(.) with ARM64_SW_TTBR0_PAN=y we apply phys_to_ttbr
to a value that already has an ASID inserted into the upper bits. For
52-bit PA configurations this then can give us TTBR0_EL1 registers that
cause translation table walks to attempt to access non-zero PA[51:48]
spuriously. Ultimately leading to a Synchronous External Abort on level
1 translation.
This patch re-arranges the logic in cpu_do_switch_mm(.) such that
phys_to_ttbr is called before the ASID is inserted into the TTBR0 value.
Fixes: 6b88a32c7af6 ("arm64: kpti: Fix the interaction between ASID switching and software PAN")
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
0 files changed, 0 insertions, 0 deletions