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authorArnd Bergmann2018-03-27 14:18:41 +0200
committerArnd Bergmann2018-03-27 14:18:41 +0200
commit97be8ab23dc1eacf4ea96649520463b9cf597a45 (patch)
tree85ea485c081c43459840642cb8e2d53b69681c10 /Documentation/devicetree/bindings/arm
parentMerge tag 'v4.16-next-dts32' of ssh://gitolite.kernel.org/pub/scm/linux/kerne... (diff)
parentarm64: dts: mt2712: Add auxadc device node. (diff)
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Merge tag 'v4.16-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt
Pull "ARM: mediatek: dts64 updates for v4.16-next" from Matthias Brugger: - mt2712e add auxadc devcie mt7622: - fix clock bindings description - add nodes for mmc, usb, SATA, PCI, ethernet, cpufreq, PMIC mt6380, pinctrl, scpsys and clock devices * tag 'v4.16-next-dts64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: mt2712: Add auxadc device node. dt-bindings: clock: mediatek: add missing required #reset-cells arm64: dts: mt7622: add mmc related device nodes arm64: dts: mt7622: add usb device nodes arm64: dts: mt7622: add SATA device nodes arm64: dts: mt7622: add PCIe device nodes arm64: dts: mt7622: add ethernet device nodes arm64: dts: mt7622: add flash related device nodes arm64: dts: mt7622: add SoC and peripheral related device nodes arm64: dts: mt7622: turn uart0 clock to real ones arm64: dts: mt7622: add cpufreq related device nodes arm64: dts: mt7622: add PMIC MT6380 related nodes arm64: dts: mt7622: add pinctrl related device nodes arm64: dts: mt7622: add power domain controller device nodes arm64: dts: mt7622: add clock controller device nodes
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt2
3 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 6cc7840ff37a..8f5335b480ac 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -9,6 +9,7 @@ Required Properties:
- "mediatek,mt2701-ethsys", "syscon"
- "mediatek,mt7622-ethsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The ethsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
index d5d5f1227665..7fe5dc6097a6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-pciesys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The PCIESYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
index 00760019da00..b8184da2508c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -8,6 +8,7 @@ Required Properties:
- compatible: Should be:
- "mediatek,mt7622-ssusbsys", "syscon"
- #clock-cells: Must be 1
+- #reset-cells: Must be 1
The SSUSBSYS controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};