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| author | Thierry Reding | 2016-04-12 17:07:35 +0200 |
|---|---|---|
| committer | Rob Herring | 2016-04-20 00:25:18 +0200 |
| commit | f43521e9521133c169fe4b9255fb0917baf5ec84 (patch) | |
| tree | 534e3d772386d08af5618430b8b3820c8646ae77 /Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | |
| parent | of: Add Inforce Computing to vendor prefix list (diff) | |
| download | kernel-qcow2-linux-f43521e9521133c169fe4b9255fb0917baf5ec84.tar.gz kernel-qcow2-linux-f43521e9521133c169fe4b9255fb0917baf5ec84.tar.xz kernel-qcow2-linux-f43521e9521133c169fe4b9255fb0917baf5ec84.zip | |
dt-bindings: tegra: Remove 0, prefix from unit-addresses
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses
with more than one cell.
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt index ee7e5fd4a50b..63f9d8277d48 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt @@ -50,7 +50,7 @@ Required properties for I2C mode: Example: -clock@0,70110000 { +clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0 0x70110000 0 0x100>, /* DFLL control */ <0 0x70110000 0 0x100>, /* I2C output control */ |