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| author | Alexandre Belloni | 2018-03-22 16:15:23 +0100 |
|---|---|---|
| committer | Marc Zyngier | 2018-03-22 16:52:27 +0100 |
| commit | c927d74ec0319abb0b232adf9dbe4e7be3791328 (patch) | |
| tree | 99e3b3e6c902e22fb1dbee21b982ed9c2d533bc2 /Documentation/devicetree/bindings/interrupt-controller | |
| parent | irqchip/gic-v3: Probe for SCR_EL3 being clear before resetting AP0Rn (diff) | |
| download | kernel-qcow2-linux-c927d74ec0319abb0b232adf9dbe4e7be3791328.tar.gz kernel-qcow2-linux-c927d74ec0319abb0b232adf9dbe4e7be3791328.tar.xz kernel-qcow2-linux-c927d74ec0319abb0b232adf9dbe4e7be3791328.zip | |
dt-bindings: interrupt-controller: Add binding for the Microsemi Ocelot interrupt controller
Add the Device Tree binding documentation for the Microsemi Ocelot
interrupt controller that is part of the ICPU. It is connected directly to
the MIPS core interrupt controller.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt new file mode 100644 index 000000000000..b47a8a02b17b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt @@ -0,0 +1,22 @@ +Microsemi Ocelot SoC ICPU Interrupt Controller + +Required properties: + +- compatible : should be "mscc,ocelot-icpu-intr" +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. +- interrupt-parent : phandle of the CPU interrupt controller. +- interrupts : Specifies the CPU interrupt the controller is connected to. + +Example: + + intc: interrupt-controller@70000070 { + compatible = "mscc,ocelot-icpu-intr"; + reg = <0x70000070 0x70>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; |