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| author | Icenowy Zheng | 2017-01-26 16:48:51 +0100 |
|---|---|---|
| committer | Linus Walleij | 2017-01-30 16:26:28 +0100 |
| commit | 838adb576d4a3da03d4e35a3149dc015dfeec299 (patch) | |
| tree | 6e2770a3ca7679691fff79e88e1269041fff8366 /Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | |
| parent | pinctrl: intel: Add Intel Gemini Lake pin controller support (diff) | |
| download | kernel-qcow2-linux-838adb576d4a3da03d4e35a3149dc015dfeec299.tar.gz kernel-qcow2-linux-838adb576d4a3da03d4e35a3149dc015dfeec299.tar.xz kernel-qcow2-linux-838adb576d4a3da03d4e35a3149dc015dfeec299.zip | |
drivers: pinctrl: add driver for Allwinner H5 SoC
Based on the Allwinner H5 datasheet and the pinctrl driver of the
backward-compatible H3 this introduces the pin multiplex assignments for
the H5 SoC.
H5 introduced some more pin functions (e.g. three more groups of TS
pins, and one more groups of SIM pins) than H3.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index de1378b4efad..7c85dca4221a 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -23,6 +23,7 @@ Required properties: "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" "allwinner,sun50i-a64-pinctrl" + "allwinner,sun50i-h5-r-pinctrl" "nextthing,gr8-pinctrl" - reg: Should contain the register physical address and length for the |