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author | Magnus Damm | 2014-12-03 13:18:03 +0100 |
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committer | Thomas Gleixner | 2015-01-26 11:38:22 +0100 |
commit | e03f9088e22ca7e2b0de826466540e2527518e52 (patch) | |
tree | 78e192dab008ea8852d9fb57836338d160ed96af /Documentation/devicetree/of_selftest.txt | |
parent | Merge branch 'linus' into irq/core (diff) | |
download | kernel-qcow2-linux-e03f9088e22ca7e2b0de826466540e2527518e52.tar.gz kernel-qcow2-linux-e03f9088e22ca7e2b0de826466540e2527518e52.tar.xz kernel-qcow2-linux-e03f9088e22ca7e2b0de826466540e2527518e52.zip |
irqchip: renesas-intc-irqpin: r8a7779 IRLM setup support
Add r8a7779 specific support for IRLM bit configuration
in the INTC-IRQPIN driver. Without this code we need
special workaround code in arch/arm/mach-shmobile.
The IRLM bit for the INTC hardware exists on various
older SH-based SoCs and is used to select between two
modes for the external interrupt pins IRQ0 to IRQ3:
IRLM = 0: (default from reset on r8a7779)
In this mode the pins IRQ0 to IRQ3 are used together
to give a value between 0 and 15 to the SoC. External
logic is required for masking. This mode is not
supported by the INTC-IRQPIN driver.
IRLM = 1: (needs this patch or configuration elsewhere)
In this mode IRQ0 to IRQ3 operate as 4 individual
external interrupt pins. In this mode the SMSC ethernet
chip can be used via IRQ1 on r8a7779 Marzen. This mode
is the only supported mode by the INTC-IRQPIN driver.
For this patch to work the r8a7779 DTS needs to pass
the ICR0 register as the last register bank.
Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: horms@verge.net.au
Cc: jason@lakedaemon.net
Link: http://lkml.kernel.org/r/20141203121803.5936.35881.sendpatchset@w520
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'Documentation/devicetree/of_selftest.txt')
0 files changed, 0 insertions, 0 deletions