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| author | Geert Uytterhoeven | 2017-10-12 10:54:22 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven | 2017-10-20 10:59:54 +0200 |
| commit | d454cecc637b90996ab15b2e61a6cc51b7e1463c (patch) | |
| tree | c131cc6fa0e4df8111a4bcb473cf0df408009eab /Documentation/devicetree | |
| parent | clk: renesas: r8a77995: Correct parent clock of INTC-AP (diff) | |
| download | kernel-qcow2-linux-d454cecc637b90996ab15b2e61a6cc51b7e1463c.tar.gz kernel-qcow2-linux-d454cecc637b90996ab15b2e61a6cc51b7e1463c.tar.xz kernel-qcow2-linux-d454cecc637b90996ab15b2e61a6cc51b7e1463c.zip | |
clk: renesas: rz: clk-rz is meant for RZ/A1
The RZ family of Renesas SoCs has several different subfamilies (RZ/A,
RZ/G, RZ/N, and RZ/T). Clarify that the renesas,rz-cpg-clocks DT
bindings and clk-rz driver apply to RZ/A1 only.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt index bb5d942075fb..8ff3e2774ed8 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt +++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt @@ -1,6 +1,6 @@ -* Renesas RZ Clock Pulse Generator (CPG) +* Renesas RZ/A1 Clock Pulse Generator (CPG) -The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable +The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable CPU and GPU clocks, and several fixed ratio dividers. The CPG also provides a Clock Domain for SoC devices, in combination with the CPG Module Stop (MSTP) Clocks. |